Programmable delay line with glitch suppression
AssigneeAnalog Devices, Inc.
InventorJohn KENNEY
Life of this patent
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Abstract
There is disclosed herein programmable delay lines and control methods having glitch suppression. In particular, the programmable delay lines may include latches that are triggered based on a trigger event of an input signal (which is often an edge of the input signal). The programmable delay lines may include one or more latches coupled between capacitor and transistor subassemblies and the latches, where the latches cause a delay between the time the trigger event arrives at the capacitor and transistor subassemblies and the latches. The delay can prevent the latches from updating at the same time that the edge of the input signal arrives at the capacitor and transistor subassemblies, which can suppress glitches that can causes errors in operation.
Claims21
1-20. (canceled)
A delay system, comprising:
- a static phase offset (SPO) delay element to receive an input signal, the SPO delay element comprising:
- a capacitor and transistor subassembly coupled an input of the SPO delay element, the capacitor and transistor subassembly to apply a delay to the input signal when the capacitor and transistor subassembly is conducting;
- a buffer coupled to an output of the SPO delay element;
- and
- a latch coupled to the buffer and to receive an output of the buffer as a trigger input, wherein an output of the latch is to control conduction of the capacitor and transistor subassembly;
- and
- a shift register coupled to the SPO delay element, the shift register to provide a control word to the SPO delay element, wherein the control word defines a value of the output of the latch.
A method for controlling a delay system for a signal, comprising:
- providing a first control word to a first static phase offset (SPO) delay element;
- providing a second control word to a second SPO delay element, wherein the second control word is within a single bit difference of the first control word;
- and
- updating a value of the first control word based on a strobe signal and a shift signal, wherein updating of the value of the first control word includes maintaining the second control word within the single bit difference of the first control word.
A delay system, comprising:
- a first static phase offset (SPO) delay element to receive a first control word;
- and
- a second static phase offset (SPO) delay element to receive a second control word, wherein the second control word is within a single bit difference of the first control word;
- wherein the first SPO delay element is further to update a value of the first control word based on a strobe signal and a shift signal, and to maintain the first control word within the single bit difference of the second control word.
Dependencies are inferred from the claim text.