# US 2023/0069801 A1 · Metal Gate Structure of High-Voltage Device and Method for Making the Same

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- Number: US 2023/0069801 A1
- Document ID: US20230069801A1
- Status: Published application
- Kind: A1
- Application number: 17/848,531
- Filed: 2022-06-24
- Published: 2023-03-02
- Earliest claimed: 2021-08-24
- Assignees: Shanghai Huali Integrated Circuit Corporation
- Applicants: Shanghai Huali Integrated Circuit Corporation
- Inventors: Yu Xia; Zhibin He
- Web page: https://patentgrep.com/patent/US20230069801A1

## CPC

- H10D 64/01354: {passivation or protection of the electrode, e.g. using re-oxidation}
- H10D 64/0112: {using conductive layers comprising silicides}
- H10D 64/01316: {the conductor comprising a layer of elemental metal contacting the insulator, e.g. Ta, W, Mo or Al}
- H10D 64/01326: {Aspects related to lithography, isolation or planarisation of the conductor}
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 64/62: Electrodes ohmically coupled to a semiconductor
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

The present application provides a metal gate structure of a high-voltage device and a method for making the same, forming a dummy gate on the gate oxide layer, wherein the dummy gate is composed of a plurality of polysilicon structures spaced apart from each other; forming a protective layer on sidewalls of the plurality of polysilicon structures and on the gate oxide layer between the polysilicon structures; performing covering with an insulating layer to fill a region between the polysilicon structures, wherein the filled region forms an insulating structure; removing the polysilicon structure to form a groove; forming a metal layer, wherein the metal layer covers the insulating structure and fills the groove; and polishing the surface of the metal layer, wherein the insulating structure, the protective layer, and the metal layer form a metal gate with a planarized surface.

## Claims

### Claim 1

A method for making a metal gate structure of a high-voltage device, comprising:
step 1, providing a silicon substrate, the silicon substrate being provided with an active region, forming a gate oxide layer on the active region, and forming a dummy gate on the gate oxide layer, wherein the dummy gate is composed of a plurality of polysilicon structures spaced apart from each other;
step 2, forming a protective layer on sidewalls of the plurality of polysilicon structures and on the gate oxide layer between the polysilicon structures;
step 3, performing covering with an insulating layer to fill a region between the polysilicon structures, wherein the filled region forms an insulating structure;
step 4, removing the polysilicon structure to form a groove;
step 5, forming a metal layer, wherein the metal layer covers the insulating structure and fills the groove; and
step 6: polishing a surface of the metal layer, wherein the insulating structure, the protective layer, and the metal layer form a metal gate with a planarized surface.

### Claim 2 (depends on 1)

The method for making the metal gate structure of the high-voltage device according to claim 1, wherein the method of forming the dummy gate on the gate oxide layer in step 1 is: first forming a polysilicon layer covering the gate oxide layer on the active region; and then etching the polysilicon layer to form the dummy gate.

### Claim 3 (depends on 1)

The method for making the metal gate structure of the high-voltage device according to claim 1, wherein the method of forming the protective layer on the sidewalls of the plurality of polysilicon structures in step 2 comprises: (1) depositing a protective layer covering surfaces of the plurality of polysilicon structures and a surface of the gate oxide layer between the polysilicon structures; and (2) removing the protective layer on a top of the plurality of polysilicon structures by means of photolithography and etching, so as to remain the protective layer on the sidewalls of the plurality of polysilicon structures and on the surface of the gate oxide layer between the polysilicon structures.

### Claim 4 (depends on 1)

The method for making the metal gate structure of the high-voltage device according to claim 1, wherein before forming the insulating layer in step 3, a NiSi layer is first formed on an upper surface of the active region at two sides of the gate oxide layer.

### Claim 5 (depends on 1)

The method for making the metal gate structure of the high-voltage device according to claim 1, wherein the insulating layer in step 3 is a silicon oxide layer or a silicon nitride layer.

### Claim 6 (depends on 1)

The method for making the metal gate structure of the high-voltage device according to claim 1, wherein the polishing in step 6 is chemical mechanical polishing.

### Claim 7

A metal gate structure of a high-voltage device, comprising:
a silicon substrate;
an active region provided on the silicon substrate;
a gate oxide layer formed on the active region;
a NiSi layer formed on the active region at two sides of the gate oxide layer;
insulating structures spaced apart from each other and formed on the gate oxide layer;
a groove formed by a region between the insulating structures;
a protective layer formed on a sidewall of the groove and a bottom of the insulating structure; and
metal filling the groove, wherein the insulating structure, the protective layer, and a metal layer form a metal gate with a planarized surface.