# US 2023/0069737 A1 · Semiconductor package and manufacturing method thereof

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- Number: US 2023/0069737 A1
- Document ID: US20230069737A1
- Status: Published application
- Kind: A1
- Application number: 17/458,610
- Filed: 2021-08-27
- Published: 2023-03-02
- Earliest claimed: 2021-08-27
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company, Ltd.
- Inventors: Wei-Chung Chang; Ming-Che Ho; Hung-Jui Kuo
- Web page: https://patentgrep.com/patent/US20230069737A1

## CPC

- H10P 72/74: {using temporarily an auxiliary support}
- H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
- H10P 14/44: Physical vapour deposition [PVD]
- H10W 20/057: {by selectively depositing, e.g. by using selective CVD or plating}
- H10W 70/614: {the multiple chips being integrally enclosed}
- H10W 74/131: {the semiconductor body being only partially enclosed}
- H10P 72/7424: {used as a support during the manufacture of self-supporting substrates}
- H10P 72/7436: {used to support a device or a wafer when forming electrical connections thereto}
- H10W 70/05: of insulating or insulated package substrates, or of interposers, or of redistribution layers (manufacture or treatment of leadframes H10W70/04)
- H10W 70/099: {Connecting interconnections to insulating or insulated package substrates, interposers or redistribution layers}
- H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40)
- H10W 70/611: {for connecting multiple chips together}
- H10W 70/685: comprising multiple insulating layers
- H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts}
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor package includes a substrate, a composite seed-barrier layer, a routing via, and a semiconductor die. The substrate has a through hole formed therethrough. The composite seed-barrier layer extends on sidewalls of the through hole and includes a first barrier layer, a seed layer, and a second barrier layer sequentially stacked on the sidewalls of the through hole. The routing via fills the through hole and is separated from the substrate by the composite seed-barrier layer. The semiconductor die is electrically connected to the routing via. Along the sidewalls of the through holes, at a level height corresponding to half of a total thickness of the substrate, the seed layer is present as inclusions of seed material surrounded by barrier material of the first barrier layer and the second barrier layer.

## Claims

### Claim 1

A semiconductor package, comprising:
a substrate, having a through hole formed therethrough;
a composite seed-barrier layer, extending on sidewalls of the through hole and comprising a first barrier layer, a seed layer, and a second barrier layer sequentially stacked on the sidewalls of the through hole;
a routing via, filling the through hole and separated from the substrate by the composite seed-barrier layer; and
a semiconductor die, electrically connected to the routing via,
wherein, along the sidewalls of the through hole, at a level height corresponding to half of a total thickness of the substrate, the seed layer is present as inclusions of seed material surrounded by barrier material of the first barrier layer and the second barrier layer.

### Claim 2 (depends on 1)

The semiconductor package of claim 1, wherein
the seed material comprises copper, silver, gold, nickel, titanium, alloys thereof, or a combination thereof, and
the barrier material comprises titanium, tantalum, a nitride thereof, or a combination thereof, and has a different composition than the seed material.

### Claim 3 (depends on 1)

The semiconductor package of claim 1, wherein the first barrier layer and the seed layer further extend over a first surface of the substrate, and the second barrier layer further extends on a second surface of the substrate opposite to the first surface and connected to the first surface by the sidewalls of the through holes.

### Claim 4 (depends on 3)

The semiconductor package of claim 3, wherein the composite seed-barrier layer further comprises another seed layer stacked on the second barrier layer.

### Claim 5 (depends on 3)

The semiconductor package of claim 3, further comprising a conductive block extending over the first surface of the substrate and electrically contacting the routing via, wherein the conductive block extends on sections of the seed layer, and a section of the second barrier layer is interposed between the routing via and the conductive block.

### Claim 6 (depends on 5)

The semiconductor package of claim 5, wherein the semiconductor die is disposed on the substrate beside the conductive block, and the semiconductor package further comprises:
an encapsulant, laterally wrapping the conductive block and the semiconductor die; and
conductive layers and dielectric layers extending on the encapsulated semiconductor die and conductive block, wherein the conductive layers electrically connect the conductive block to the semiconductor die.

### Claim 7 (depends on 3)

The semiconductor package of claim 3, further comprising a routing pattern extending over the second surface of the substrate and being integrally formed with the routing via.

### Claim 8

A semiconductor package, comprising:
a substrate, having a frontside surface and a backside surface opposite to the frontside surface and connected to the frontside surface by tapered sidewalls of the substrate;
a barrier layer, extending on the frontside surface and over the tapered sidewalls of the substrate;
a seed layer, extending on the barrier layer;
a patterned conductive trace, comprising a routing pattern extending on a section of the seed layer disposed over the frontside surface and a routing via formed as a single piece with the routing pattern and extending on a section of the seed layer disposed over the tapered sidewalls; and
a conductive block, extending over the backside surface and electrically connected to the patterned conductive trace,
wherein sections of the barrier layer and the seed layer are disposed between the conductive block and the routing via.

### Claim 9 (depends on 8)

The semiconductor package of claim 8, wherein the substrate is a ceramic substrate.

### Claim 10 (depends on 8)

The semiconductor package of claim 8, further comprising:
another barrier layer, extending on the backside surface of the substrate; and
another seed layer, extending on the other barrier layer over the backside surface of the substrate,
wherein a section of the barrier layer is disposed between the routing via and the other barrier layer and directly contacts the other barrier layer.

### Claim 11 (depends on 10)

The semiconductor package of claim 10, wherein the conductive block is disposed on the other seed layer, and between the routing via and the conductive block are stacked, in order, the seed layer, the barrier layer, the other barrier layer, and the other seed layer.

### Claim 12 (depends on 10)

The semiconductor package of claim 10, wherein the section of the barrier layer disposed between the routing via and the other barrier layer is located at a same level height as the backside surface of the substrate.

### Claim 13 (depends on 8)

The semiconductor package of claim 8, further comprising:
another barrier layer, extending on the backside surface of the substrate; and
another seed layer, extending on the other barrier layer over the backside surface of the substrate,
wherein sections of the other barrier layer and of the other seed layer are disposed between the tapered sidewalls of the substrate and the barrier layer in proximity of the backside surface of the substrate.

### Claim 14

A manufacturing method of a semiconductor package, comprising:
sputtering a first barrier material on a substrate having through holes extending from a frontside surface to a backside surface, wherein the first barrier material is sputtered towards the frontside surface;
sputtering a first seed material on the sputtered first barrier material towards the frontside surface;
bonding a backside film to the backside surface of the substrate, whereby the through holes are blocked at one end by the backside film;
plating a first conductive material on the sputtered seed material after the backside film is bonded to the substrate, whereby the plated first conductive material is formed in the through holes and over the frontside surface of the substrate; and
removing the backside film after the first conductive material is plated.

### Claim 15 (depends on 14)

The manufacturing method of claim 14, wherein the backside film is bonded to the substrate before sputtering the first barrier material, whereby the first barrier material is also deposited on the backside film at the one ends of the through holes.

### Claim 16 (depends on 15)

The manufacturing method of claim 15, further comprising:
sputtering a second barrier material on the substrate towards the backside surface of the substrate after the backside film is removed;
sputtering a second seed material on the second barrier material towards the backside surface of the substrate; and
plating a second conductive material on the sputtered second seed material.

### Claim 17 (depends on 14)

The manufacturing method of claim 14, further comprising:
sputtering a second barrier material on the substrate towards the backside surface of the substrate before sputtering the first barrier material; and
sputtering a second seed material on the second barrier material towards the backside surface of the substrate before sputtering the first barrier material,
wherein at least a portion of the first barrier material is sputtered on the second seed material.

### Claim 18 (depends on 17)

The manufacturing method of claim 17, further comprising plating a second conductive material on the sputtered second seed material after the backside film is removed.

### Claim 19 (depends on 18)

The manufacturing method of claim 18, wherein the backside film is bonded to the substrate after sputtering the first seed material, whereby in correspondence of the through holes, the plated first conductive material directly contacts the plated second conductive material.

### Claim 20 (depends on 17)

The manufacturing method of claim 17, wherein the through holes have an aspect ratio in the range of 1.5 to 5.