# US 2023/0069697 A1 · Methods for forming dielectric layer in forming semiconductor device

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- Number: US 2023/0069697 A1
- Document ID: US20230069697A1
- Status: Published application
- Kind: A1
- Application number: 17/498,337
- Filed: 2021-10-11
- Published: 2023-03-02
- Earliest claimed: 2021-09-01
- Assignees: Yangtze Memory Technologies Co., Ltd.
- Applicants: Yangtze Memory Technologies Co., Ltd.
- Inventors: Yonggang Yang; Xiaohong Zhou
- Web page: https://patentgrep.com/patent/US20230069697A1

## CPC

- H10P 50/73: {using masks for insulating materials}
- H10B 41/27: the channels comprising vertical portions, e.g. U-shaped channels
- H10B 41/50: characterised by the boundary region between the core region and the peripheral circuit region
- H10B 43/27: the channels comprising vertical portions, e.g. U-shaped channels
- H10B 43/50: characterised by the boundary region between the core and peripheral circuit regions
- H10P 50/283: {by chemical means}
- H10P 95/062: {involving a dielectric removal step}
- H10P 95/064: {the removal being chemical etching}
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10B: ELECTRONIC MEMORY DEVICES

## Abstract

Methods for forming a 3D memory device are provided. A method includes the following operations. A stack structure is formed in a staircase region and an array region. A dielectric material layer is formed over the array region and the staircase region. An etch mask layer is coated over the dielectric material layer. The etch mask layer, on a first surface away from the dielectric material layer, is planarized. The dielectric material layer and a remaining portion of the etch mask layer are etched to form a dielectric layer over the staircase region and the array region.

## Claims

### Claim 1

A method for forming a three-dimensional (3D) memory device, comprising:
forming a stack structure over a staircase region and an array region;
forming a dielectric material layer over the array region and the staircase region;
forming an etch mask layer over the dielectric material layer;
planarizing a first surface of the etch mask layer away from the dielectric material layer; and
etching the dielectric material layer and a remaining portion of the etch mask layer to form a dielectric layer over the staircase region and the array region.

### Claim 2 (depends on 1)

The method of claim 1, wherein the first surface of the etch mask layer is level.

### Claim 3 (depends on 1)

The method of claim 1, wherein the etch mask layer comprises photoresist.

### Claim 4 (depends on 1)

The method of claim 1, wherein planarizing the etch mask layer comprises performing a chemical mechanical polishing (CMP) on the etch mask layer until a portion of the dielectric material layer over the array region is exposed.

### Claim 5 (depends on 4)

The method of claim 4, further comprising etching the remaining portion of the etch mask layer in the staircase region in a same etching process that etches the dielectric material layer.

### Claim 6 (depends on 1)

The method of claim 1, wherein an etch rate on the dielectric material layer is higher than an etch rate on the etch mask layer.

### Claim 7 (depends on 6)

The method of claim 6, wherein a ratio of the etch rate on the dielectric material layer over the etch rate on the etch mask layer ranges from about 20:1 to about 100:1.

### Claim 8 (depends on 1)

The method of claim 1, wherein etching the dielectric material layer and the remaining portion of the etch mask layer comprises a dry etching process.

### Claim 9 (depends on 1)

The method of claim 1, further comprising fully removing the remaining portion of the etch mask layer over the staircase region after the etching of the dielectric material layer.

### Claim 10 (depends on 9)

The method of claim 9, wherein removing the remaining portion of the etch mask layer comprises an ashing process.

### Claim 11 (depends on 1)

The method of claim 1, further comprising planarizing the dielectric layer over the array region and the staircase region.

### Claim 12 (depends on 1)

The method of claim 1, wherein forming the etch mask layer comprises a spin coating process.

### Claim 13

A method for forming a three-dimensional (3D) memory device, comprising:
forming a stack structure over a staircase region and an array region;
forming a dielectric material layer over the array region and the staircase region;
forming an etch mask portion over a portion of the dielectric material layer over the staircase region; and
etching the dielectric material layer and the etch mask portion to form a dielectric layer over the staircase region and the array region.

### Claim 14 (depends on 13)

The method of claim 13, wherein the etch mask portion comprises a photoresist portion.

### Claim 15 (depends on 13)

The method of claim 13, wherein:
forming the etch mask portion comprises forming an etch mask layer over the dielectric material layer over the staircase region and the array region; and
planarizing the etch mask layer to fully remove a portion of the etch mask layer over the array region.

### Claim 16 (depends on 15)

The method of claim 15, wherein planarizing the etch mask layer comprises performing a chemical mechanical polishing (CMP) on the etch mask layer until the portion of the dielectric material layer over the array region is exposed.

### Claim 17 (depends on 13)

The method of claim 13, wherein the etch mask portion and the dielectric material layer are etched in a same etching process.

### Claim 18 (depends on 13)

The method of claim 13, wherein an etch rate on the dielectric material layer is higher than an etch rate on the etch mask portion.

### Claim 19 (depends on 18)

The method of claim 18, wherein a ratio of the etch rate on the dielectric material layer over the etch rate on the etch mask portion ranges from about 20:1 to about 100:1.

### Claim 20 (depends on 13)

The method of claim 13, wherein etching the dielectric material layer and the etch mask portion comprises a dry etching process.