# US 2023/0068359 A1 · Compact static random-access memory structure

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- Number: US 2023/0068359 A1
- Document ID: US20230068359A1
- Status: Published application
- Kind: A1
- Application number: 17/461,426
- Filed: 2021-08-30
- Published: 2023-03-02
- Earliest claimed: 2021-08-30
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company, Ltd.
- Inventors: Ruey-Wen Chang; Feng-Ming Chang; Ping-Wei Wang
- Web page: https://patentgrep.com/patent/US20230068359A1

## CPC

- H10B 10/12: {comprising a MOSFET load element}
- G11C 11/412: using field-effect transistors only
- H10D 84/8311: {the IGFETs characterised by having different channel structures}
- H10D 84/853: {comprising FinFETs}
- H10B: ELECTRONIC MEMORY DEVICES
- G11C: STATIC STORES (semiconductor memory devices H10B)
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A static random-access memory (SRAM) structure and the manufacturing method thereof are disclosed. An exemplary SRAM structure includes a first source/drain (S/D) feature and a second S/D feature formed in an interlayer dielectric layer (ILD) of a bit cell region of the SRAM structure, a frontside via electrically connecting to the first S/D feature, and a first backside via electrically connecting to the second S/D feature. The first S/D feature and the second S/D feature are of a same type.

## Claims

### Claim 1

A static random-access memory (SRAM) structure comprising:
a first source/drain (S/D) feature and a second S/D feature formed in an interlayer dielectric layer (ILD) of a bit cell region of the SRAM structure, wherein the first S/D feature and the second S/D feature are of a same type;
a frontside via electrically connecting to the first S/D feature; and
a first backside via electrically connecting to the second S/D feature.

### Claim 2 (depends on 1)

The SRAM structure of claim 1, further comprising:
a third S/D feature formed in the ILD, wherein the third S/D feature is of a type different than the type of the first and the second S/D features; and
a second backside via electrically connecting to the third S/D feature.

### Claim 3 (depends on 2)

The SRAM structure of claim 2, wherein the first S/D feature electrically connects to the drain voltage (VD), the second S/D feature electrically connects to the negative supply voltage (Vss), and the third S/D feature electrically connects to the positive supply voltage (Vdd).

### Claim 4 (depends on 2)

The SRAM structure of claim 2, wherein the first and second S/D features are N-type S/D features, and the third S/D feature is a P-type S/D feature.

### Claim 5 (depends on 1)

The SRAM structure of claim 1, further comprising a S/D contact formed between the first S/D feature and the frontside via.

### Claim 6 (depends on 1)

The SRAM structure of claim 1, further comprising semiconductor fins formed along sidewalls of the first and second S/D features; and
gate structures formed over the semiconductor fins.

### Claim 7 (depends on 1)

The SRAM structure of claim 1, further comprising an edge region free of a tap cell.

### Claim 8

A static random-access memory (SRAM) structure comprising:
a first source/drain (S/D) feature and a second S/D feature formed in a bit cell region of the SRAM structure, wherein the first S/D feature and the second S/D feature are of different types;
a first backside via electrically connecting to the first S/D feature; and
a second backside via electrically connecting to the second S/D feature.

### Claim 9 (depends on 8)

The SRAM structure of claim 8, further comprising an edge region free of a tap cell.

### Claim 10 (depends on 9)

The SRAM structure of claim 9, wherein a width of the edge region is equal or less than 4 critical poly pitches (CPP).

### Claim 11 (depends on 8)

The SRAM structure of claim 8, further comprising:
a third S/D feature formed in the bit cell region of the SRAM structure, wherein the third S/D feature is of the same type as the first S/D feature;
a S/D contact formed over the third S/D feature; and
a frontside via formed over the S/D contact and electrically connecting to the third S/D feature.

### Claim 12 (depends on 11)

The SRAM structure of claim 11, wherein the first S/D feature and the third S/D feature are N-type S/D features and the second S/D feature is a P-type S/D feature.

### Claim 13 (depends on 12)

The SRAM structure of claim 12, wherein the first S/D feature electrically connects to a negative supply voltage (Vss), the second S/D feature electrically connects to a positive supply voltage (Vdd), and the third S/D feature electrically connects to a drain voltage (VD).

### Claim 14 (depends on 11)

The SRAM structure claim 11, further comprising:
semiconductor fins formed along sidewalls of the first, second, and third S/D features; and
gate structures formed over the semiconductor fins and electrically connecting to a gate voltage (VG).

### Claim 15

A method for forming a static random-access memory (SRAM) structure, comprising:
receiving a substrate including a first region and a second region;
forming a first semiconductor fin in the first region of the substrate and a second semiconductor fin in the second region of the substrate, wherein the first semiconductor fin and the second semiconductor fin are separated by an isolation structure;
forming a first source/drain (S/D) feature over the first semiconductor fin and a second S/D feature over the second semiconductor fin;
connecting the second S/D feature to a frontside conductive feature; and
connecting the first S/D feature to a first backside conductive feature.

### Claim 16 (depends on 15)

The method of claim 15, further comprising:
forming a third semiconductor fin in the first region and a fourth semiconductor fin in the second region, wherein the first semiconductor fin and the second semiconductor fin are of a same type, and the third semiconductor fin and the fourth semiconductor fin are of another same type which is different from the type of the first semiconductor fin and the second semiconductor fin.

### Claim 17 (depends on 16)

The method of claim 16, further comprising:
epitaxially growing a third source/drain (S/D) feature over the third semiconductor fin; and
connecting the third S/D feature with a second backside conductive feature.

### Claim 18 (depends on 17)

The method of claim 17, wherein:
the frontside conductive feature is connected to a drain voltage (VD);
the first backside conductive feature is connected to a negative supply voltage (Vss); and
the second backside conductive feature is connected to a positive supply voltage.

### Claim 19 (depends on 15)

The method of claim 15, wherein connecting the second S/D feature to a frontside conductive feature includes:
forming a S/D contact over the second S/D feature;
forming a frontside via contacting the S/D contact; and
forming a frontside metal line contacting the frontside via.

### Claim 20 (depends on 15)

The method of claim 15, wherein connecting the first S/D feature to a first backside conductive feature includes:
removing the substrate and the isolation structure;
forming a backside via contacting the first S/D feature; and
forming a backside power rail contacting the backside via.