# US 2023/0068097 A1 · Base layout cell > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2023/0068097 A1 - Document ID: US20230068097A1 - Status: Published application - Kind: A1 - Application number: 17/459,485 - Filed: 2021-08-27 - Published: 2023-03-02 - Earliest claimed: 2021-08-27 - Assignees: Taiwan Semiconductor Manufacturing Company, Ltd. - Applicants: Taiwan Semiconductor Manufacturing Co., Ltd. - Inventors: Shang-Hsuan CIOU; Chih-Liang Chen; Hui-Zhong Zhuang; Chi-Yu Lu; Kuang-Ching Chang - Web page: https://patentgrep.com/patent/US20230068097A1 ## CPC - G06F 30/392: Floor-planning or layout, e.g. partitioning or placement - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract Systems, methods and devices are provided, which can include an engineering change order (ECO) base. A base layout cell includes metal layer regions, conductive gate patterns arranged above metal layer regions; oxide definition (OD) patterns, metal-zero layer over oxide-definition (metal-zero) patterns, at least one cut metal layer (CMD) pattern; and at least one via region. The base layout cell can be implemented in at least two non-identical functional cells. A first functional cell of the at least two non-identical functional cells includes first interconnection conductive patterns arranged connecting metal-zero structures corresponding to at least two metal-zero patterns in a first layout, and a second functional cell of the at least two non-identical functional cells includes second interconnection conductive patterns arranged connecting metal-zero structures corresponding to at least two metal-zero patterns in a second layout. ## Claims ### Claim 1 A method, comprising: placing a base layout cell in a layout, wherein the base layout cell comprises: first and second metal layer patterns extending in a first direction; a plurality of active area layer patterns between the first metal layer pattern and the second metal layer pattern, wherein the plurality of active layer patterns extend in the first direction; a plurality of conductive gate layer patterns extending in a second direction perpendicular to the first direction and traversing over the first and second metal layer patterns and over the plurality of active area layer patterns; a plurality of contact layer patterns extending in the second direction between two conductive gate layer patterns of the plurality of conductive gate layer patterns, wherein at least one contact layer pattern of the plurality of contact layer patterns traverses over at least one active area layer pattern of the plurality of active layer patterns; and a cut metal layer extending in the first direction between two active area layer patterns of the plurality of active area layer patterns, wherein the cut metal layer is between at least two conductive gate layer patterns; connecting one or more of the first and second metal layer patterns, the plurality of active area layer patterns, the plurality of conductive gate layer patterns, the plurality of contact layer patterns to represent a first circuit; and defining the first circuit based on a base mark of the base layout cell. ### Claim 2 (depends on 1) The method of claim 1, wherein the placing the base layout cell comprises selecting the base layout cell from a plurality of base layout cells applicable to an inverter functional cell, an NAND functional cell, a NOR functional cell, or an AND-OR-INVERTER functional cell. ### Claim 3 (depends on 2) The method of claim 2, wherein the placing the base layout cell comprises selecting the base layout cell based on a layout cell pitch value. ### Claim 4 (depends on 1) The method of claim 1, wherein the first circuit comprises one or more layout patterns common to a plurality of non-identical functional cell layouts. ### Claim 5 (depends on 1) The method of claim 1, wherein the connecting one or more of the first and second metal layer patterns comprises routing one or more of the first and second metal layer patterns to a power supply, ground, or a combination thereof. ### Claim 6 (depends on 1) The method of claim 1, further comprising connecting the first circuit to a second circuit, wherein at least one of the placing the base layout cell in the layout, the connecting the one or more of the first and second metal layer patterns, the plurality of active area layer patterns, the plurality of conductive gate layer patterns, the plurality of contact layer patterns to represent a first circuit, and the connecting the first circuit to the second circuit is performed by one or more processors. ### Claim 7 (depends on 6) The method of claim 6, wherein the connecting the first circuit to the second circuit comprises arranging the first circuit and the second circuit based on a combined cell pitch of the first circuit and the second circuit. ### Claim 8 (depends on 7) The method of claim 7, wherein the arranging the first circuit and the second circuit comprises arranging the first circuit and the second circuit with an electronic design automation tool. ### Claim 9 A base layout cell, comprising: first and second metal layer patterns extending in a first direction; a plurality of active area layer patterns between the first metal layer pattern and the second metal layer pattern, wherein the plurality of active layer patterns extend in the first direction; a plurality of conductive gate layer patterns extending in a second direction perpendicular to the first direction and traversing over the first and second metal layer patterns and over the plurality of active area layer patterns; a plurality of contact layer patterns extending in the second direction between two conductive gate layer patterns of the plurality of conductive gate layer patterns, wherein at least one contact layer pattern of the plurality of contact layer patterns traverses over at least one active area layer pattern of the plurality of active layer patterns; and a cut metal layer extending in the first direction between two active area layer patterns of the plurality of active area layer patterns, wherein the cut metal layer is between at least two conductive gate layer patterns, and wherein the base layout cell comprises one or more layout patterns common to a plurality of non-identical functional cell layouts. ### Claim 10 (depends on 9) The base layout cell of claim 9, wherein the base layout cell comprises at least one layout pattern representative of an inverter functional cell, an NAND functional cell, a NOR functional cell, or an AND-OR-INVERTER functional cell. ### Claim 11 (depends on 10) The base layout cell of claim 10, wherein the base layout cell omits interconnections that are not commonly shared between at least two functional cell layout patterns. ### Claim 12 (depends on 9) The base layout cell of claim 9, wherein the base layout cell has a layout cell pitch value corresponding to at least one layout pattern having an arrangement common to a plurality of functional cell layouts, and wherein the base layout cell is selected from a plurality of base layout cells based on the cell pitch value. ### Claim 13 (depends on 9) The base layout cell of claim 9, wherein the first metal layer pattern and the second metal layer pattern are isolated from each other, and wherein the base layout cell is arranged to be implemented in a first circuit by connecting one or more of the first and second metal layer patterns, the plurality of active area layer patterns, the plurality of conductive gate layer patterns, and the plurality of contact layer patterns to represent the first circuit. ### Claim 14 (depends on 13) The base layout cell of claim 13, further comprising a base mark associated with a boundary of the first circuit, wherein the base mark indicates a boundary of at least one layout pattern with an arrangement common to a plurality of functional cell layouts. ### Claim 15 A non-transitory computer-readable medium having instructions stored therein, which when executed by a processor of a hand held device, causes the processor to perform operations, the operations comprising: placing, by the processor, a base layout cell in a layout, wherein the base layout cell comprises: first and second metal layer patterns extending in a first direction; a plurality of active area layer patterns between the first metal layer pattern and the second metal layer pattern, wherein the plurality of active layer patterns extend in the first direction; a plurality of conductive gate layer patterns extending in a second direction perpendicular to the first direction and traversing over the first and second metal layer patterns and over the plurality of active area layer patterns; a plurality of contact layer patterns extending in the second direction between two conductive gate layer patterns of the plurality of conductive gate layer patterns, wherein at least one contact layer pattern of the plurality of contact layer patterns traverses over at least one active area layer pattern of the plurality of active layer patterns; and a cut metal layer extending in the first direction between two active area layer patterns of the plurality of active area layer patterns, wherein the cut metal layer is between at least two conductive gate layer patterns; connecting, by the processor, one or more of the first and second metal layer patterns, the plurality of active area layer patterns, the plurality of conductive gate layer patterns, the plurality of contact layer patterns to represent a first circuit; and connecting, by the processor, the first circuit to a second circuit. ### Claim 16 (depends on 15) The non-transitory computer-readable medium of claim 15, wherein the placing the base layout cell comprises selecting the base layout cell based on a layout cell pitch value. ### Claim 17 (depends on 15) The non-transitory computer-readable medium of claim 15, wherein the base layout cell comprises one or more layout patterns common to a plurality of non-identical functional cell layouts. ### Claim 18 (depends on 15) The non-transitory computer-readable medium of claim 15, wherein the connecting the first circuit to the second circuit comprises arranging the first circuit and the second circuit based on a combined cell pitch of the first circuit and the second circuit. ### Claim 19 (depends on 15) The non-transitory computer-readable medium of claim 15, wherein the operations further comprise defining, by the processor, the first circuit based on a base mark of the base layout cell. ### Claim 20 (depends on 15) The non-transitory computer-readable medium of claim 15, wherein the operations further comprise routing, by the processor, one or more of the first and second metal layer patterns to a power supply, ground, or a combination thereof.