# US 2023/0067752 A1 · Semiconductor devices and methods of manufacturing thereof

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- Number: US 2023/0067752 A1
- Document ID: US20230067752A1
- Status: Published application
- Kind: A1
- Application number: 17/460,208
- Filed: 2021-08-28
- Published: 2023-03-02
- Earliest claimed: 2021-08-28
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company, Ltd.
- Inventors: Ya-Yi Tsai; Yi-Chun Chen; Wei-Han Chen; Wei-Ting Guo; Shu-Yuan Ku
- Web page: https://patentgrep.com/patent/US20230067752A1

## CPC

- H10D 30/0243: {using dummy structures having essentially the same shapes as the semiconductor bodies, e.g. to provide stability}
- H10D 30/62: Fin field-effect transistors [FinFET]
- H10D 30/6211: {having fin-shaped semiconductor bodies integral with the bulk semiconductor substrates}
- H10D 62/115: {Dielectric isolations, e.g. air gaps}
- H10D 84/0151: {Manufacturing their isolation regions}
- H10D 84/0158: {the components including FinFETs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/834: {comprising FinFETs}
- H10D 62/121: {oriented parallel to substrates}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A method of fabricating a semiconductor device is described. A plurality of semiconductor fins is formed in a first region on a substrate. An isolation region is formed around the plurality of semiconductor fins. Dummy fins are formed extending above the isolation region and laterally adjacent the plurality of semiconductor fins. A first etch is performed to etch the plurality of semiconductor fins such that a top surface of the plurality of semiconductor fins has a same height as a top surface of the isolation region. A second etch is performed selectively etching the isolation region to form a first recess in the isolation region laterally adjacent the semiconductor fins. A third etch is performed selectively etching the plurality of semiconductor fins to remove the plurality of semiconductor fins and to etch a second recess through the isolation region into the semiconductor substrate.

## Claims

### Claim 1

A method of fabricating a semiconductor device, comprising:
forming a plurality of semiconductor fins in a first region on a substrate;
forming an isolation region around the plurality of semiconductor fins, a top surface of the plurality of semiconductor fins being above a top surface of the dielectric isolation;
performing a first etch to etch the plurality of semiconductor fins such that a top surface of the plurality of semiconductor fins has a same height as a top surface of the isolation region;
performing a second etch selectively etching the isolation region to form a first recess in the isolation region laterally adjacent the semiconductor fins; and
performing a third etch selectively etching the plurality of semiconductor fins to remove the plurality of semiconductor fins and to etch a second recess through the isolation region into the semiconductor substrate.

### Claim 2 (depends on 1)

The method of claim 1, further comprising:
forming dummy fins extending above the isolation region and laterally adjacent the plurality of semiconductor fins; and
forming a dielectric material to fill the second recess and to contact side surfaces of the dummy fins.

### Claim 3 (depends on 1)

The method of claim 1, wherein the first etch is performed with a different etchant than the second etch.

### Claim 4 (depends on 2)

The method of claim 2, wherein the first etch is performed with a same etchant as the third etch.

### Claim 5 (depends on 1)

The method of claim 1, wherein the plurality of semiconductor fins are tapered with a width increasing from a bottom to a top of the plurality of semiconductor fins.

### Claim 6 (depends on 1)

The method of claim 1, further comprising forming at least one semiconductor fin in a second region.

### Claim 7 (depends on 1)

The method of claim 1, wherein the third etch includes a first sub-etch to remove a top portion of the fins in the first region, and a second sub-etch to etch the second recess.

### Claim 8

A method of fabricating a semiconductor device, comprising:
forming a plurality of semiconductor fins in a first region on a substrate;
forming an isolation region around the plurality of semiconductor fins, a top surface of the plurality of semiconductor fins being above a top surface of the isolation region;
performing a first etch using a first etchant to etch the plurality of semiconductor fins such that a top surface of the plurality of semiconductor fins has a same height as a top surface of the isolation region;
performing a second etch using a second etchant, different from the first etchant, to etch the isolation region to form a first recess in the isolation region laterally adjacent the semiconductor fins; and
performing a third etch using a third etchant, different from the second etchant, to etch the plurality of semiconductor fins to remove the plurality of semiconductor fins and etch a second recess through the isolation region into the semiconductor substrate.

### Claim 9 (depends on 8)

The method of claim 8, further comprising:
forming dummy fins extending above the isolation region and laterally adjacent the plurality of semiconductor fins; and
forming a dielectric material to fill the second recess and to contact side surfaces of the dummy fins.

### Claim 10 (depends on 8)

The method of claim 8, wherein the first etchant is a same as the third etchant.

### Claim 11 (depends on 8)

The method of claim 8, wherein the first etchant includes at least HBr.

### Claim 12 (depends on 8)

The method of claim 8, wherein the second etchant is fluorine based.

### Claim 13 (depends on 12)

The method of claim 12, wherein the second etchant includes at least one of CF4 or C4F6.

### Claim 14 (depends on 8)

The method of claim 8, wherein the plurality of semiconductor fins are tapered with a width increasing from a bottom to a top of the plurality of semiconductor fins.

### Claim 15

A semiconductor device, comprising:
a semiconductor substrate;
an isolation region disposed on the semiconductor substrate;
a plurality of dummy fins in a first region extending from the isolation region; and
a dielectric material extending through the isolation region and into the semiconductor substrate, the dielectric material disposed between the plurality of dummy fins;
a height of the isolation region on an inner side of the plurality of dummy fins being less than a height of the isolation region on an outer side of the plurality of dummy fins.

### Claim 16 (depends on 15)

The semiconductor device of claim 15, wherein the plurality of dummy fins are formed of a dielectric material.

### Claim 17 (depends on 15)

The semiconductor device of claim 15, further comprising at least one semiconductor fin.

### Claim 18 (depends on 17)

The semiconductor device of claim 17, further comprising a metal gate disposed over the at least one fin.

### Claim 19 (depends on 17)

The semiconductor device of claim 17, further comprising source and drain structures disposed in the at least one semiconductor fin.

### Claim 20 (depends on 19)

The semiconductor device of claim 19, further comprising an interlevel dielectric disposed above the source and drain structures.