# US 2023/0067573 A1 · Predicated vector load micro-operation > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2023/0067573 A1 - Document ID: US20230067573A1 - Status: Published application - Kind: A1 - Application number: 17/459,130 - Filed: 2021-08-27 - Published: 2023-03-02 - Earliest claimed: 2021-08-27 - Assignees: Arm Limited - Applicants: Arm Limited - Inventors: . ABHISHEK RAJA - Web page: https://patentgrep.com/patent/US20230067573A1 ## CPC - G06F 9/30043: {LOAD or STORE instructions; Clear instruction} - G06F 9/30018: {Bit or string instructions} - G06F 9/30036: {Instructions to perform operations on packed data, e.g. vector, tile or matrix operations} - G06F 9/30038: {using a mask} - G06F 9/30072: {to perform conditional operations, e.g. using predicates or guards} - G06F 9/30145: {Instruction analysis, e.g. decoding, instruction word fields} - G06F 9/3836: {Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution} - G06F 9/3842: {Speculative instruction execution} - G06F 9/3861: {Recovery, e.g. branch miss-prediction, exception handling (error detection or correction G06F11/00)} - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract A predicated vector load micro-operation specifies a load target address, a destination vector register for which active vector elements of the destination vector register are to be loaded with data associated with addresses identified based on the load target address, and a predicate operand indicative of whether each vector element of the destination vector register is active or inactive. A predetermined type of predicated vector load micro-operation can be issued to the processing circuitry before the predicate operand is determined to meet an availability condition, and if issued in this way memory access circuitry can determine, based on the load target address, whether the predetermined type of predicated vector load micro-operation satisfies a predetermined condition, and if the predetermined condition is unsatisfied, perform a complete vector load assuming all vector elements of the destination vector register are active vector elements, independent of whether the predicate operand when available identifies any inactive vector element of the destination vector register. ## Claims ### Claim 1 An apparatus comprising: processing circuitry to perform data processing in response to micro-operations decoded from instructions, the processing circuitry comprising memory access circuitry to control issuing of memory access requests; and issue circuitry to control issuing of the micro-operations to the processing circuitry based on whether operands of the micro-operations meet an availability condition; in which: in response to a predicated vector load micro-operation specifying a load target address, a destination vector register for which active vector elements of the destination vector register are to be loaded with data associated with addresses identified based on the load target address, and a predicate operand indicative of whether each vector element of the destination vector register is active or inactive: when the predicated vector load micro-operation is a predetermined type of predicated vector load micro-operation, the issue circuitry is capable of issuing the predetermined type of predicated vector load micro-operation to the processing circuitry before the predicate operand is determined to meet the availability condition; and when the predetermined type of predicated vector load micro-operation is issued to the processing circuitry before the predicate operand meets the availability condition, the memory access circuitry is configured to: determine, based on the load target address, whether the predetermined type of predicated vector load micro-operation satisfies a predetermined condition; and in response to determining that the predetermined condition is unsatisfied for the predetermined type of predicated vector load micro-operation, perform a complete vector load assuming all vector elements of the destination vector register are active vector elements, independent of whether the predicate operand when available identifies any inactive vector element of the destination vector register. ### Claim 2 (depends on 1) The apparatus according to claim 1, in which: in response to the memory access circuitry determining that the predetermined condition is satisfied when the predetermined type of predicated vector load micro-operation is issued to the processing circuitry before the predicate operand meets the availability condition, the memory access circuitry is configured to reject the predetermined type of predicated vector load micro-operation and the issue circuitry is configured to re-issue the predetermined type of predicated vector load micro-operation to the processing circuitry. ### Claim 3 (depends on 1) The apparatus according to claim 1, in which the issue circuitry is configured to re-issue the predetermined type of predicated vector load micro-operation to the processing circuitry when the predicate operand is determined to meet the availability condition. ### Claim 4 (depends on 1) The apparatus according to claim 1, in which: in response to determining that the predetermined condition is unsatisfied for the predetermined type of predicated vector load micro-operation, the memory access circuitry is configured to allow the complete vector load to proceed without being flushed even when the predicate operand when available indicates at least one inactive vector element. ### Claim 5 (depends on 1) The apparatus according to claim 1, in which the memory access circuitry is configured to determine that the predetermined condition is satisfied for the predetermined type of predicated vector load micro-operation when the memory access circuitry determines that performing the complete vector load in response to the predetermined type of predicated vector load micro-operation would cause at least one address-dependent memory-access-related side-effect. ### Claim 6 (depends on 5) The apparatus according to claim 5, in which when the predetermined type of predicated vector load micro-operation is processed when the predicate operand is already available, the memory access circuitry is configured to suppress the at least one address-dependent memory-access-related side-effect being caused by a load associated with an inactive vector element of the destination vector register indicated by the predicate operand. ### Claim 7 (depends on 1) The apparatus according to claim 1, in which the memory access circuitry is configured to determine that the predetermined condition is satisfied for the predetermined type of predicated vector load micro-operation when the memory access circuitry determines based on the load target address that, if the complete vector load was performed, the complete vector load would cause a fault. ### Claim 8 (depends on 1) The apparatus according to claim 1, in which the memory access circuitry is configured to determine that the predetermined condition is satisfied for the predetermined type of predicated vector load micro-operation, when the memory access circuitry determines based on the load target address that, if the complete vector load was performed, the complete vector load would cause an access to a device region of memory address space allocated for communication with a device other than a memory storage device. ### Claim 9 (depends on 1) The apparatus according to claim 1, in which the memory access circuitry is configured to determine that the predetermined condition is satisfied for the predetermined type of predicated vector load micro-operation, when the memory access circuitry determines based on the load target address that if the complete vector load was performed, the complete vector load would cause a memory access to an address defined as a watchpoint address for which a diagnostic operation is to be triggered when an access to the watchpoint address is requested. ### Claim 10 (depends on 1) The apparatus according to claim 1, in which: when the predicated vector load micro-operation is a second type of predicated vector load micro-operation, the issue circuitry is configured to defer issuing of the second type of predicated vector load micro-operation to the processing circuitry until the predicate operand is determined to meet the availability condition. ### Claim 11 (depends on 1) The apparatus according to claim 1, in which: in response to a predicated vector store micro-operation specifying a store target address, a source vector register for which data from active vector elements of the source vector register is to be stored to memory locations associated with addresses identified based on the target address, and a store predicate operand indicative of whether each vector element of the source vector register is active or inactive: the issue circuitry is configured to defer issuing the predicated vector store micro-operation to the processing circuitry until the store predicate operand is determined to meet the availability condition. ### Claim 12 (depends on 1) The apparatus according to claim 1, comprising instruction decoding circuitry to decode instructions to generate the micro-operations to be issued to the processing circuitry; in which: in response to decoding a predicated-loop-body instruction, the instruction decoding circuitry is configured to generate a plurality of micro-operations for controlling the processing circuitry to perform an iteration of a predicated loop body comprising: determining a variable number of bytes to be processed in the iteration: performing a predicated vector load operation predicated based on the variable number of bytes; performing at least one further predicated operation which is dependent on the predicated vector load operation and is predicated based on the variable number of bytes; and updating, based on the variable number of bytes, a remaining bytes parameter indicative of a number of bytes remaining to be processed; and in response to decoding the predicated-loop-body instruction, the instruction decoding circuitry is configured to generate the predetermined type of predicated vector load micro-operation for performing the predicated vector load operation of the predicated loop body. ### Claim 13 (depends on 12) The apparatus according to claim 12, in which the at least one further predicated operation is one of: a predicated vector store operation; and a predicated vector compare operation. ### Claim 14 (depends on 12) The apparatus according to claim 12, in which in response to the predicated-loop-body instruction, the instruction decoding circuitry is configured to generate at least one micro-operation to control the processing circuitry to determine the variable number of bytes based on alignment, with respect to an alignment boundary, of at least one of: a load target address of the predicated vector load operation; and where the at least one further predicated operation is a predicated vector store operation, a store target address of the predicated vector store operation. ### Claim 15 (depends on 12) The apparatus according to claim 12, in which in response to the predicated-loop-body instruction, the instruction decoding circuitry is configured to generate at least one micro-operation to control the processing circuitry to determine the variable number of bytes based on the remaining bytes parameter. ### Claim 16 (depends on 12) The apparatus according to claim 12, in which the iteration of the predicated loop body also comprises controlling whether a further iteration of the predicated loop body is to be performed based on whether a loop termination condition is satisfied by the remaining bytes parameter. ### Claim 17 (depends on 1) The apparatus according to claim 1, comprising instruction decoding circuitry to decode instructions to generate the micro-operations to be issued to the processing circuitry; in which: the instruction decoding circuitry is configured to generate the predetermined type of predicated vector load micro-operation in response to an instruction for implementing a string.h C library function which acts on a string stored in memory. ### Claim 18 (depends on 1) The apparatus according to claim 1, comprising instruction decoding circuitry to decode instructions to generate the micro-operations to be issued to the processing circuitry; in which: the instruction decoding circuitry is configured to generate the predetermined type of predicated vector load micro-operation in response to a memory copy instruction for copying data from a first memory region to a second memory region. ### Claim 19 A method comprising: controlling issuing of micro-operations, decoded from instructions, to processing circuitry, where the controlling of issuing is based on whether operands of the micro-operations meet an availability condition, and the processing circuitry comprises memory access circuitry to control issuing of memory access requests; and in response to a predicated vector load micro-operation specifying a load target address, a destination vector register for which active vector elements of the destination vector register are to be loaded with data associated with addresses derived from the load target address, and a predicate operand indicative of whether each vector element of the destination vector register is active or inactive, when the predicated vector load micro-operation is a predetermined type of predicated vector load micro-operation: issuing the predetermined type of predicated vector load micro-operation to the processing circuitry before the predicate operand is determined to meet the availability condition; determining, based on the load target address, whether the predetermined type of predicated vector load micro-operation satisfies a predetermined condition; and in response to determining that the predetermined condition is unsatisfied for the predetermined type of predicated vector load micro-operation, performing a complete vector load assuming all vector elements of the destination vector register are active vector elements, independent of whether the predicate operand when available identifies any inactive vector element of the destination vector register. ### Claim 20 A non-transitory computer-readable medium to store computer-readable code for fabrication of an apparatus comprising: processing circuitry to perform data processing in response to micro-operations decoded from instructions, the processing circuitry comprising memory access circuitry to control issuing of memory access requests; and issue circuitry to control issuing of the micro-operations to the processing circuitry based on whether operands of the micro-operations meet an availability condition; in which: in response to a predicated vector load micro-operation specifying a load target address, a destination vector register for which active vector elements of the destination vector register are to be loaded with data associated with addresses identified based on the load target address, and a predicate operand indicative of whether each vector element of the destination vector register is active or inactive: when the predicated vector load micro-operation is a predetermined type of predicated vector load micro-operation, the issue circuitry is capable of issuing the predetermined type of predicated vector load micro-operation to the processing circuitry before the predicate operand is determined to meet the availability condition; and when the predetermined type of predicated vector load micro-operation is issued to the processing circuitry before the predicate operand meets the availability condition, the memory access circuitry is configured to: determine, based on the load target address, whether the predetermined type of predicated vector load micro-operation satisfies a predetermined condition; and in response to determining that the predetermined condition is unsatisfied for the predetermined type of predicated vector load micro-operation, perform a complete vector load assuming all vector elements of the destination vector register are active vector elements, independent of whether the predicate operand when available identifies any inactive vector element of the destination vector register.