# US 2023/0067352 A1 · Semiconductor device and electronic device

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 2023/0067352 A1
- Document ID: US20230067352A1
- Status: Published application
- Kind: A1
- Application number: 17/797,233
- Filed: 2021-03-01
- Published: 2023-03-02
- Earliest claimed: 2020-03-13
- Assignees: Semiconductor Energy Laboratory Co., Ltd.
- Applicants: Semiconductor Energy Laboratory Co., Ltd.
- Inventors: Kazuaki OHSHIMA; Hitoshi KUNITAKE
- Web page: https://patentgrep.com/patent/US20230067352A1

## CPC

- H10W 90/00: Package configurations
- H03K 19/018514: {with at least one differential stage (H03K19/018528 and H03K19/018542 take precedence)}
- H03K 19/094: using field-effect transistors
- H10D 30/6755: {Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate}
- H10D 84/0128: {Manufacturing their channels}
- H10D 84/0158: {the components including FinFETs}
- H10D 84/08: using combinations of technologies, e.g. using both Si and SiC technologies or using both Si and Group III-V technologies
- H10D 84/8311: {the IGFETs characterised by having different channel structures}
- H10D 84/83138: {the IGFETs characterised by having different shapes or dimensions of their gate conductors}
- H10D 86/441: {Interconnections, e.g. scanning lines}
- H10D 86/60: wherein the TFTs are in active matrices
- H10D 88/00: Three-dimensional [3D] integrated devices
- H10W 70/611: {for connecting multiple chips together}
- H10W 70/65: Shapes or dispositions of interconnections
- H10D 30/6734: {having gate electrodes arranged on both top and bottom sides of the channel, e.g. dual-gate TFTs}
- H10D 87/00: Integrated devices comprising both bulk components and either SOI or SOS components on the same substrate
- H10W 74/019: {using temporary auxiliary substrates (H10W74/017 takes precedence)}
- H10W 74/117: {the substrate having spherical bumps for external connection}
- H10W 90/28: the stacked chips having different sizes, e.g. chip stacks having a pyramidal shape
- H10W 90/291: {characterised by containers, encapsulations, or other housings for the stacked chips}
- H10W 90/722: {between stacked chips}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A semiconductor device being capable of high-speed data transmission and having a reduced circuit area is provided. The semiconductor device includes a semiconductor chip, an external terminal, and a layer including two facing surfaces. The semiconductor chip is provided on one surface side of the layer, and the external terminal is provided on the other surface side of the layer at least in a region not overlapping with the semiconductor chip. The semiconductor chip includes a first circuit including a first transistor, and the layer includes a second circuit including a second transistor. The first circuit is electrically connected to the second circuit, and the second circuit is electrically connected to the external terminal. The second transistor includes a metal oxide in a channel formation region. Note that the second circuit may be a CML circuit. In addition, an insulator may be provided above the one surface of the layer and on a side surface of the semiconductor chip.

## Claims

### Claim 1

A semiconductor device comprising:
a semiconductor chip comprising a first circuit, a first external terminal, and a layer comprising a second circuit,
wherein the semiconductor chip is provided adjacent to one surface of the layer,
wherein the first external terminal is provided adjacent to the other surface of the layer,
wherein the first circuit comprises a first transistor and is electrically connected to the second circuit,
wherein the second circuit comprises a second transistor and is electrically connected to the first external terminal,
wherein a material of a channel formation region of the first transistor is different from a material of a channel formation region of the second transistor,
wherein the channel formation region of the second transistor comprises a metal oxide, and
wherein the metal oxide comprises indium and gallium.

### Claim 2 (depends on 1)

The semiconductor device according to claim 1,
wherein the second circuit is a current mode logic circuit.

### Claim 3 (depends on 1)

The semiconductor device according to claim 1,
wherein an insulator covers the one surface of the layer and a side surface and a top surface of the semiconductor chip.

### Claim 4 (depends on 1)

The semiconductor device according to claim 1, further comprising a second external terminal,
wherein the semiconductor chip further comprises a first connection terminal and a second connection terminal,
wherein the first circuit is electrically connected to the second circuit through the first connection terminal, and
wherein a pitch width between the first external terminal and the second external terminal is larger than a pitch width between the first connection terminal and the second connection terminal.

### Claim at position 5

-6. (canceled)

### Claim 7 (depends on 1)

The semiconductor device according to claim 1, wherein the metal oxide further comprises zinc.

### Claim 8 (depends on 1)

The semiconductor device according to claim 1, wherein the channel formation region of the first transistor comprises silicon.

### Claim 9 (depends on 1)

The semiconductor device according to claim 1, wherein the channel formation region of the first transistor and the channel formation region of the second transistor overlap each other.

### Claim 10 (depends on 1)

The semiconductor device according to claim 1, wherein the first transistor and the first external terminal are stacked with the second transistor therebetween.

### Claim 11 (depends on 1)

The semiconductor device according to claim 1, wherein the first external terminal comprises a bump.