# US 2023/0066718 A1 · Processor with a hash cryptographic algorithm and data processing thereof

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 2023/0066718 A1
- Document ID: US20230066718A1
- Status: Published application
- Kind: A1
- Application number: 17/837,695
- Filed: 2022-06-10
- Published: 2023-03-02
- Earliest claimed: 2021-09-01
- Assignees: Shanghai Zhaoxin Semiconductor Co., Ltd.
- Applicants: Shanghai Zhaoxin Semiconductor Co., Ltd.
- Inventors: Zhenhua HUANG; Yingbing GUAN; Yanting LI
- Web page: https://patentgrep.com/patent/US20230066718A1

## CPC

- H04L 9/0643: {Hash functions, e.g. MD5, SHA, HMAC or f9 MAC}
- H04L 9/0841: {involving Diffie-Hellman or related key agreement protocols}
- H04L 9/3066: {involving algebraic varieties, e.g. elliptic or hyper-elliptic curves}
- H04L 9/3247: {involving digital signatures}
- H04L 2209/20: Manipulating the length of blocks of bits, e.g. padding or block truncation
- H04L: TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION (arrangements common to telegraphic and telephonic communication H04M)

## Abstract

A processor with a Hash cryptographic algorithm and a data processing method are shown. In response to one single Hash cryptographic instruction of an instruction set architecture, the processor reads a first storage space within a system memory to obtain an input message of a limited length, and processes the input message in accordance with the Hash cryptographic algorithm to generate a final Hash value of a specific length.

## Claims

### Claim 1

A processor with a Hash cryptographic algorithm, characterized in that:
in response to a single Hash cryptographic instruction of an instruction set architecture, the processor reads a first storage space within a system memory to obtain an input message of a limited length, and processes the input message in accordance with the Hash cryptographic algorithm to generate a final Hash value of a specific length.

### Claim 2 (depends on 1)

The processor with the Hash cryptographic algorithm as claimed in claim 1, comprising:
a first register, recording an input message length of the input message;
wherein according to the input message length, the processor divides the input message to generate at least one message block, and performs message expansion and iterative compression on each message block to update a Hash value block by block, and to finally generate the final Hash value.

### Claim 3 (depends on 2)

The processor with the Hash cryptographic algorithm as claimed in claim 2, further comprising:
a second register, recording a message padding flag;
when the message padding flag shows that message padding is required for the input message, the processor pads the input message till the size of the padded input message is a multiple of the size of one message block, for dividing the padded input message to generate the at least one message block.

### Claim 4 (depends on 2)

The processor with the Hash cryptographic algorithm as claimed in claim 2, wherein:
when a message padding flag shows that message padding is required for the input message, the input message length is represented by a byte number, and the processor pads the input message based on the byte number;
when the message padding flag shows that message padding is not required for the input message, the input message length is represented by a message block number, and each message block is N bytes, where N is a positive integer.

### Claim 5 (depends on 4)

The processor with the Hash cryptographic algorithm as claimed in claim 4, further comprising:
a third register, storing an input message pointer pointing to the first storage space storing the input message; and
in response to the single Hash cryptographic instruction, the processor reads the input message from the system memory by referring to the third register.

### Claim 6 (depends on 5)

The processor with the Hash cryptographic algorithm as claimed in claim 5, further comprising:
a second register, recording the message padding flag;
when finishing the Hash cryptographic algorithm on the input message, the processor modifies the input message pointer in the third register to point to a higher address of the system memory;
when the message padding flag recorded in the second register shows that message padding is required for the input message, an address increment made on the input message pointer is the same as a value stored in the first register; and
when the message padding flag recorded in the second register shows that message padding is not required for the input message, an address increment made on the input message pointer is N times a value stored in the first register.

### Claim 7 (depends on 5)

The processor with the Hash cryptographic algorithm as claimed in claim 5, further comprising:
a fourth register, storing a Hash value pointer, pointing to a second storage space within the system memory;
wherein:
prior to the processor processes the input message in accordance with the Hash cryptographic algorithm, an initial Hash value is prepared in the second storage space;
in response to the single Hash cryptographic instruction, the processor reads the initial Hash value from the system memory by referring to the fourth register, transforms the initial Hash value into the final Hash value based on the input message, and programs the final Hash value into the second storage space by referring to the fourth register to replace the initial Hash value.

### Claim 8 (depends on 5)

The processor with the Hash cryptographic algorithm as claimed in claim 5, further comprising:
a fourth register; and
a cryptographic unit, comprising an internal register;
wherein:
in response to the single Hash cryptographic instruction, the processor transforms an initial Hash value into the final Hash value based on the input message, stores the final Hash value in the internal register, and programs a register number representing the internal register into the fourth register.

### Claim 9 (depends on 8)

The processor with the Hash cryptographic algorithm as claimed in claim 8, wherein:
prior to processing the input message in accordance with the Hash cryptographic algorithm, the processor fills the fourth register with zero.

### Claim 10 (depends on 4)

The processor with the Hash cryptographic algorithm as claimed in claim 4, further comprising:
a third register, storing an information pointer, pointing to a third storage space within the system memory where an input message pointer and a Hash value pointer are stored;
wherein:
the input message pointer pointing to the first storage space storing the input message;
the Hash value pointer pointing to a second storage space within the system memory;
prior to the processor processes the input message in accordance with the Hash cryptographic algorithm, an initial Hash value is prepared in the second storage space;
in response to the single Hash cryptographic instruction, the processor obtains the input message pointer and the Hash value pointer by referring to the third register, reads the input message and the initial Hash value from the system memory as indicated by the input message pointer and the Hash value pointer, transforms the initial Hash value into the final Hash value based on the input message, and programs the final Hash value into the second storage space as indicated by the Hash value pointer to replace the initial Hash value.

### Claim 11 (depends on 4)

The processor with the Hash cryptographic algorithm as claimed in claim 4, wherein:
the single Hash cryptographic instruction includes a first field and a second field;
the first field stores an input message pointer pointing to the first storage space storing the input message;
the second field stores a Hash value pointer pointing to a second storage space within the system memory;
prior to the processor processes the input message in accordance with the Hash cryptographic algorithm, an initial Hash value is prepared in the second storage space;
in response to the single Hash cryptographic instruction, the processor reads the input message and the initial Hash value from the system memory as indicated by the input message pointer and the Hash value pointer, transforms the initial Hash value into the final Hash value based on the input message, and programs the final Hash value into the second storage space as indicated by the Hash value pointer to replace the initial Hash value.

### Claim 12 (depends on 4)

The processor with the Hash cryptographic algorithm as claimed in claim 4, wherein:
when finishing the Hash cryptographic algorithm on the input message, if the message padding flag recorded in a second register shows that message padding is required for the input message, the processor does not change the input message length recorded in the first register; and
when finishing the Hash cryptographic algorithm on the input message, if the message padding flag recorded in the second register shows that message padding is not required for the input message, the processor resets the input message length recorded in the first register to zero.

### Claim 13 (depends on 12)

The processor with the Hash cryptographic algorithm as claimed in claim 12, wherein:
when finishing the Hash cryptographic algorithm on the input message, if the message padding flag recorded in the second register shows that message padding is required for the input message, the processor updates the second register by the input message length obtained from the first register; and
when finishing the Hash cryptographic algorithm on the input message, if the message padding flag recorded in the second register shows that message padding is not required for the input message, the processor does not change the second register.

### Claim 14 (depends on 1)

The processor with the Hash cryptographic algorithm as claimed in claim 1, further comprising:
a cryptographic unit;
a set of architectural registers;
a microcode storage device, storing microcode; and
a decoder, generating a plurality of microinstructions based on the microcode in response to the single Hash cryptographic instruction;
wherein:
according to the microinstructions, the set of architectural registers is defined, read and updated, and the cryptographic unit uses the set of architectural registers to process the input message in accordance with the Hash cryptographic algorithm.

### Claim 15 (depends on 14)

The processor with the Hash cryptographic algorithm as claimed in claim 14, wherein:
when a message padding flag shows that message padding is required for the input message, according to the microinstructions, the input message is padded till the size of the padded input message is a multiple of the size of one message block.

### Claim 16 (depends on 15)

The processor with the Hash cryptographic algorithm as claimed in claim 15, wherein:
according to the microinstructions, the input message whose size is a multiple of the size of one message block or the padded input message is divided by the size of one message block to generate at least one message block.

### Claim 17 (depends on 16)

The processor with the Hash cryptographic algorithm as claimed in claim 16, wherein:
the cryptographic unit includes a Hash cryptographic acceleration engine;
the microinstructions decoded from the single Hash cryptographic instruction include an engine driving microinstruction; and
in response to the engine driving microinstruction, the Hash cryptographic acceleration engine performs message expansion and iterative compression on each message block to update a Hash value block by block, and thereby an initial Hash value is transformed into the final Hash value.

### Claim 18 (depends on 14)

The processor with the Hash cryptographic algorithm as claimed in claim 14, wherein:
when a message padding flag shows that message padding is required for the input message, according to the microinstructions, the input message is padded to generate the padded input message, which is m′:
m′=m, 1, k{0}, 64{len}
where m is the input message, k is an integer, len is a bit length of m, m′ includes m, 1-bit ‘1’, k-bit ‘0’, and 64-bit represented len′, and (len+1+k) divided by 512 results in a remainder 448.

### Claim 19 (depends on 18)

The processor with the Hash cryptographic algorithm as claimed in claim 18, wherein:
according to the microinstructions, the input message whose size is a multiple of bits or the padded input message is divided into units of 512 bits, to generate n message blocks, B(0) to B(n−1), where n is an integer.

### Claim 20 (depends on 19)

The processor with the Hash cryptographic algorithm as claimed in claim 19, wherein:
the cryptographic unit includes a Hash cryptographic acceleration engine;
the microinstructions decoded from the single Hash cryptographic instruction include an engine driving microinstruction;
in response to the engine driving microinstruction, the Hash cryptographic acceleration engine performs message expansion and iterative compression on each message block to update a Hash value block by block, and thereby an initial Hash value is transformed into the final Hash value;
the initial Hash value is V(0), the final Hash value is V(n); and
starting from V(0), the Hash cryptographic acceleration engine processes B(0) to B(n−1) block by block and finally generates V(n).

### Claim 21 (depends on 20)

The processor with the Hash cryptographic algorithm as claimed in claim 20, wherein the Hash cryptographic acceleration engine comprises:
hardware for message expansion, expanding each message block B(i) to 132 words W0i . . . W67i and W0i′ . . . W63i′, where i=0, . . . , (n−1).

### Claim 22 (depends on 21)

The processor with the Hash cryptographic algorithm as claimed in claim 21, wherein the Hash cryptographic acceleration engine further comprises:
hardware for iterative compression, performing 64 rounds of compression for each message block B(i), to transform the Hash value from V(i) to V(i+1), wherein each round of compression involves a Boolean function and a permutation function.

### Claim 23 (depends on 22)

The processor with the Hash cryptographic algorithm as claimed in claim 22, wherein the Hash cryptographic acceleration engine further comprises:
a first internal storage space, storing constants required in the iterative compression; and
a second internal storage space, storing V(i) for performing the 64 rounds of compression of the message block B(i), wherein V(i) in the second internal storage space is updated to V(i+1) after the 64 rounds of compression of the message block B(i).

### Claim 24

A method for performing a Hash cryptographic algorithm using a processor, comprising:
in response to a single Hash cryptographic instruction of an instruction set architecture, reading a first storage space of a system memory to obtain an input message of a limited length, and processing the input message in accordance with the Hash cryptographic algorithm to generate a final Hash value of a specific length.

### Claim 25 (depends on 24)

The method as claimed in claim 24, further comprising:
according to an input message length of the input message, dividing the input message to generate at least one message block, and performing message expansion and iterative compression on each message block to update a Hash value block by block and to finally generate the final Hash value.

### Claim 26 (depends on 25)

The method as claimed in claim 25, further comprising:
when a message padding flag shows that message padding is required for the input message, padding the input message till the size of the padded input message is a multiple of the size of one message block, for dividing the padded input message to generate at least one message block.

### Claim 27 (depends on 24)

The method as claimed in claim 24, further comprising:
in response to the single Hash cryptographic instruction, generating a plurality of microinstructions based on microcode; and
according to the microinstructions, processing the input message in accordance with the Hash cryptographic algorithm.

### Claim 28 (depends on 27)

The method as claimed in claim 27, further comprising:
when a message padding flag shows that message padding is required for the input message, according to the microinstructions, padding the input message till the size of the padded input message is a multiple of the size of one message block.

### Claim 29 (depends on 28)

The method as claimed in claim 28, further comprising:
according to the microinstructions, dividing the input message whose size is a multiple of the size of one message block or the padded input message into units of the size of one message block, to generate at least one message block.

### Claim 30 (depends on 29)

The method as claimed in claim 29, wherein the microinstructions decoded from the single Hash cryptographic instruction include an engine driving microinstruction, the method further comprising:
in response to the engine driving microinstruction, performing message expansion and iterative compression on each message block to update a Hash value block by block, and thereby an initial Hash value is transformed into the final Hash value.