# US 2023/0066705 A1 · Semiconductor devices including low-k metal gate isolation and methods of fabrication thereof

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- Number: US 2023/0066705 A1
- Document ID: US20230066705A1
- Status: Published application
- Kind: A1
- Application number: 17/460,405
- Filed: 2021-08-30
- Published: 2023-03-02
- Earliest claimed: 2021-08-30
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company, Ltd.
- Inventors: Sheng-Tsung WANG; Chia-Hao CHANG; Lin-Yu HUANG; Cheng-Chi CHUANG; Chih-Hao WANG
- Web page: https://patentgrep.com/patent/US20230066705A1

## CPC

- H10W 20/069: {by forming self-aligned vias or self-aligned contact plugs}
- H10W 20/077: {on sidewalls or on top surfaces of conductors (H10W20/076 takes precedence)}
- H10D 30/019: {of FETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 30/501: {FETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 30/6219: {characterised by the source or drain electrodes}
- H10D 62/121: {oriented parallel to substrates}
- H10D 64/01: Manufacture or treatment
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 64/251: {Source or drain electrodes for field-effect devices}
- H10D 64/514: {characterised by the insulating layers}
- H10W 20/057: {by selectively depositing, e.g. by using selective CVD or plating}
- H10W 20/0693: {by forming self-aligned vias}
- H10W 20/075: {of multilayered thin functional dielectric layers}
- H10W 20/076: {in via holes or trenches}
- H10W 20/42: Vias, e.g. via plugs
- B82Y 10/00: Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
- H10D 30/797: {being in source or drain regions, e.g. SiGe source or drain}
- H10D 62/822: comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions
- H10D 64/015: {removing at least parts of gate spacers, e.g. disposable spacers}
- H10W 20/056: {by filling conductive material into holes, grooves or trenches}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- B82Y: SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES

## Abstract

Embodiments of the present disclosure provide semiconductor devices having conductive features with reduced height and increased width, and methods for forming the semiconductor devices. Particularly, sacrificial self-aligned contact (SAC) layer and sacrificial metal contact etch stop layer (M-CESL) are used to form conductive features with reduced resistance. After formation of the conductive features, the sacrificial SAC and sacrificial M-CESL are removed and replaced with a low-k material to reduce capacitance in the device. As a result, performance of the device is improved.

## Claims

### Claim 1

A semiconductor device, comprising:
an interlayer dielectric (ILD) layer;
a first source/drain metal contact formed in the ILD layer;
a low-k dielectric layer having a top surface and a lower surface, wherein the lower surface is in contact with the ILD layer, a first portion of the low-k dielectric layer extends upward from the lower surface, and a second portion of the low-k dielectric layer extends downward from the lower surface; and
a conductive feature formed above the first source/drain metal contact, wherein a first portion of the conductive feature is embedded in the low-k dielectric layer, a second portion is embedded in the ILD layer, and the first portion is wider than the second portion.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, further comprising a gate electrode layer, wherein the second portion of the low-k dielectric layer is disposed over the gate electrode layer.

### Claim 3 (depends on 2)

The semiconductor device of claim 2, further comprising a metal gate liner disposed between the second portion of the low-k dielectric layer and the gate electrode layer.

### Claim 4 (depends on 2)

The semiconductor device of claim 2, wherein the gate electrode layer contacts the second portion of the low-k dielectric layer.

### Claim 5 (depends on 2)

The semiconductor device of claim 2, further comprising two sidewall spacers, wherein the second portion of the low-k dielectric layer is disposed between the two sidewall spacers.

### Claim 6 (depends on 5)

The semiconductor device of claim 5, wherein the sidewall spacers are in contact with the low-k dielectric layer at the lower surface.

### Claim 7 (depends on 1)

The semiconductor device of claim 1, further comprising:
a second source/drain metal contact formed in the ILD layer; and
an isolation feature in contact with the second source/drain metal contact and the lower surface of the low-k dielectric layer.

### Claim 8 (depends on 7)

The semiconductor device of claim 7, wherein the isolation feature comprises a low-k dielectric material.

### Claim 9 (depends on 8)

The semiconductor device of claim 8, wherein the isolation feature and the low-k dielectric layer are formed from the same low-k dielectric material.

### Claim 10

A semiconductor device, comprising:
first and second source/drain features;
first and second source/drain metal contacts formed above the first and second source/drain features;
a gate electrode layer disposed between the first and second source/drain features;
first and second sidewall spacers disposed between the gate electrode layer and the first and second source/drain metal contacts;
a self-aligned contact (SAC) layer disposed above the gate electrode layer, wherein the SAC layer comprises a low-k dielectric material;
a metal contact etch stop layer (M-CESL) disposed above the SAC layer; and
a conductive feature having a first portion embedded in the M-CESL layer and a second portion in contact with the first source/drain metal contact, and the first portion of the conductive feature is in contact with the SAC layer.

### Claim 11 (depends on 10)

The semiconductor device of claim 10, wherein the SAC layer and the M-CESL layer are formed from the same low-k dielectric material.

### Claim 12 (depends on 11)

The semiconductor device of claim 11, further comprising an isolation feature in contact with the second source/drain metal contact and the M-CESL layer.

### Claim 13 (depends on 12)

The semiconductor device of claim 12, wherein the isolation feature comprises a low-k dielectric material.

### Claim 14

A method for forming a semiconductor device, comprising:
depositing a sacrificial metal contact etch stop layer (M-CESL) over a first interlayer dielectric layer (ILD) having a source/drain metal contact formed therein, wherein an isolation feature is formed above the source/drain metal contact;
depositing a second ILD layer over the sacrificial M-CESL layer;
forming a contact opening by patterning the second ILD layer and the sacrificial M-CESL layer;
filling the contact opening with a conductive material;
performing a planarization process to remove the second ILD layer and the conductive material in the ILD layer to expose the sacrificial M-CESL layer;
removing the sacrificial M-CESL layer; and
depositing a low-k dielectric layer to cover the conductive material.

### Claim 15 (depends on 14)

The method of claim 14, further comprising:
forming a sacrificial self-aligned contact (SAC) layer over a gate electrode layer in the first ILD layer,
wherein forming the contact opening comprises etching the isolation feature over the source/drain metal contact using the sacrificial SAC layer as an etch stop layer.

### Claim 16 (depends on 15)

The method of claim 15, further comprising:
removing the sacrificial SAC layer to form a cavity over the gate electrode layer.

### Claim 17 (depends on 16)

The method of claim 16, wherein removing the sacrificial M-CESL layer and the sacrificial SAC layer are performed during the same etching process.

### Claim 18 (depends on 16)

The method of claim 16, wherein depositing the low-k dielectric layer comprises filling the cavity over the gate electrode layer.

### Claim 19 (depends on 15)

The method of claim 15, further comprising:
depositing a metal gate liner over the gate electrode layer prior to forming the sacrificial SAC layer.

### Claim 20 (depends on 19)

The method of claim 19, further comprising:
etching sidewall spacers on both sides of the gate electrode layer prior to depositing the metal gate liner.