# US 2023/0066352 A1 · Multi-tier deep trench capacitor and methods of forming the same

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- Number: US 2023/0066352 A1
- Document ID: US20230066352A1
- Status: Published application
- Kind: A1
- Application number: 17/458,961
- Filed: 2021-08-27
- Published: 2023-03-02
- Earliest claimed: 2021-08-27
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company Limited
- Inventors: Tao-Cheng Liu; Ying-Hsun Chen
- Web page: https://patentgrep.com/patent/US20230066352A1

## CPC

- H10D 1/042: {using deposition processes to form electrode extensions}
- H01G 4/012: Form of non-self-supporting electrodes
- H01G 4/228: Terminals
- H01G 4/30: Stacked capacitors (H01G4/33 takes precedence)
- H01G 4/33: Thin- or thick-film capacitors {(thin- or thick-film circuits; capacitors without a potential-jump or surface barrier specially adapted for integrated circuits, details thereof, multistep manufacturing processes therefor)}
- H01G 4/35: Feed-through capacitors or anti-noise capacitors
- H01G 4/385: {Single unit multiple capacitors, e.g. dual capacitor in one coil}
- H10D 1/716: {having vertical extensions}
- H10W 20/496: {Capacitor integral with wiring layers}
- H01G 4/232: electrically connecting two or more layers of a stacked or rolled capacitor
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H01G: CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE (selection of specified materials as dielectric H01B3/00; capacitors having potential barriers H10D1/62, H10K10/10)
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A first-tier capacitor assembly is formed, which includes a first alternating layer stack embedded within a first substrate and including at least two first metallic electrode layers interlaced with at least one first node dielectric layer, and first metallic bonding pads located on a first front surface. A second-tier capacitor assembly is formed, which includes a second alternating layer stack embedded within a second substrate and including at least two second metallic electrode layers interlaced with at least one second node dielectric layers, and second metallic bonding pads located on a second backside surface. The second metallic bonding pads are bonded to the first metallic bonding pads such that each of the at least two first metallic electrode layers contacts a respective one of the at least two second metallic electrode layers. A capacitor with increased capacitance is provided.

## Claims

### Claim 1

A capacitor structure comprising:
a first-tier capacitor assembly comprising a first substrate having a first front surface and a first backside surface that are parallel to each other, a first alternating layer stack embedded within the first substrate and including at least two first metallic electrode layers interlaced with at least one first node dielectric layer, and first metallic bonding pads located on the first front surface; and
a second-tier capacitor assembly comprising a second substrate having a second front surface and a second backside surface that are parallel to each other, a second alternating layer stack embedded within the second substrate and including at least two second metallic electrode layers interlaced with at least one second node dielectric layers, and second metallic bonding pads located on the second backside surface and bonded to the first metallic bonding pads;
wherein each of the at least two first metallic electrode layers contacts a respective one of the at least two second metallic electrode layers.

### Claim 2 (depends on 1)

The capacitor structure of claim 1, wherein the first front surface contacts the second backside surface within a horizontal plane in which the at least two second metallic electrode layers contact the at least two first metallic electrode layers.

### Claim 3 (depends on 1)

The capacitor structure of claim 1, wherein each layer within the second alternating layer stack continuously extends from the second front surface to the second backside surface.

### Claim 4 (depends on 3)

The capacitor structure of claim 3, wherein the first alternating layer stack extends from the first front surface into the first substrate and has a first vertical extent less than a vertical distance between the first front surface and the first backside surface.

### Claim 5 (depends on 3)

The capacitor structure of claim 3, wherein:
the first vertical extent is in a range from 2 microns to 20 microns; and
a vertical distance between the second front surface and the second backside surface is in a range from 2 microns to 20 microns.

### Claim 6 (depends on 1)

The capacitor structure of claim 1, wherein
each of the at least two first metallic electrode layers and at least one first node dielectric layer comprises a respective vertically extending portion that extends from the first front surface toward the first backside surface; and
each of the at least two second metallic electrode layers and at least one second node dielectric layers comprises a respective vertically extending portion that extends from the second front surface to the second backside surface.

### Claim 7 (depends on 1)

The capacitor structure of claim 1, further comprising:
an interconnect-level dielectric layer overlying the second substrate; and
contact via structures vertically extending through the interconnect-level dielectric layer and electrically connected to a respective one of the at least two first metallic electrode layers and to a respective one of the at least two second metallic electrode layers.

### Claim 8 (depends on 1)

The capacitor structure of claim 1, wherein:
the at least two first metallic electrode layers and the at least two second metallic electrode layers comprise a conductive metallic nitride, an elemental metal, or an intermetallic alloy;
the at least one first node dielectric layer and the at least one second node dielectric layer comprise a dielectric metal oxide or silicon nitride; and
the first substrate and the second substrate comprise semiconductor substrates.

### Claim 9 (depends on 1)

The capacitor structure of claim 1, wherein:
each layer within the first alternating layer stack laterally surrounds, or is laterally surrounded by, any other layer within the first alternating layer stack; and
each layer within the second alternating layer stack laterally surrounds, or is laterally surrounded by, any other layer within the second alternating layer stack.

### Claim 10 (depends on 1)

The capacitor structure of claim 1, wherein:
the at least two first metallic electrode layers comprise at least three first metallic electrode layers;
the at least two second metallic electrode layers comprise at least three second metallic electrode layers;
the at least one first node dielectric layer comprises at least two first node dielectric layers; and
the at least one second node dielectric layer comprise at least two second node dielectric layers.

### Claim 11

A capacitor structure comprising:
a first-tier capacitor assembly comprising a first substrate having a first front surface and a first backside surface that are parallel to each other, and a first alternating layer stack embedded within the first substrate and including at least two first metallic electrode layers interlaced with at least one first node dielectric layer, wherein one of the at least two first metallic electrode layers comprises a tab portion that extend parallel to the first front surface;
a second-tier capacitor assembly comprising a second substrate having a second front surface and a second backside surface that are parallel to each other, and a second alternating layer stack embedded within the second substrate and including at least two second metallic electrode layers interlaced with at least one second node dielectric layers; and
a contact via structure vertically extending through the second substrate and contacting a top surface of the tab portion of the one of the at least two first metallic electrode layers.

### Claim 12 (depends on 11)

The capacitor structure of claim 11, wherein each of the at least two first metallic electrode layers contacts a respective one of the at least two second metallic electrode layers at an interface at which the first front surface contacts the second backside surface.

### Claim 13 (depends on 11)

The capacitor structure of claim 11, further comprising:
first metallic bonding pads embedded in the first substrate; and
second metallic bonding pads embedded in the second substrate and bonded to a respective one of the first metallic bonding pads within a horizontal plane in which the first front surface contacts the second backside surface are located.

### Claim 14

A method of manufacturing a capacitor structure, comprising:
forming a first-tier capacitor assembly comprising a first substrate having a first front surface and a first backside surface that are parallel to each other, a first alternating layer stack embedded within the first substrate and including at least two first metallic electrode layers interlaced with at least one first node dielectric layer, and first metallic bonding pads located on the first front surface;
forming a second-tier capacitor assembly comprising a second substrate having a second front surface and a second backside surface that are parallel to each other, a second alternating layer stack embedded within the second substrate and including at least two second metallic electrode layers interlaced with at least one second node dielectric layers, and second metallic bonding pads located on the second backside surface; and
bonding the second metallic bonding pads to the first metallic bonding pads, wherein each of the at least two first metallic electrode layers contacts a respective one of the at least two second metallic electrode layers.

### Claim 15 (depends on 14)

The method of claim 14, wherein forming the first-tier capacitor assembly comprises:
forming at least one first deep trench vertically extending from the first front surface toward the first backside surface;
depositing the first alternating layer stack into the at least first deep trench and over the first front surface; and
removing portions of the first alternating layer stack from above a horizontal plane including the first front surface.

### Claim 16 (depends on 15)

The method of claim 15, wherein forming the first-tier capacitor assembly comprises:
forming pad cavities through horizontally-extending portions of the first alternating layer stack and into an upper portion of the first substrate;
depositing at least one metallic material into the pad cavities; and
removing portions of the at least one metallic material from above the horizontal plane including the first front surface concurrently with removal of the portions of the first alternating layer stack from above the horizontal plane including the first front surface, wherein remaining portions of the at least one metallic material comprise the first metallic bonding pads.

### Claim 17 (depends on 14)

The method of claim 14, wherein forming the second-tier capacitor assembly comprises;
forming at least one second deep trench into the second substrate, the at least one second deep trench having a depth less than a thickness of the second substrate;
depositing the second alternating layer stack into the at least one second deep trench; and
removing horizontally-extending portions of the second alternating layer stack from outside the at least one second deep trench.

### Claim 18 (depends on 17)

The method of claim 17, wherein:
forming the second-tier capacitor assembly comprises thinning the second substrate such that each layer within the second alternating layer stack is physically exposed on a thinned side of the second substrate; and
a planarized surface of the second substrate provided by thinning the second substrate comprises one of the second front surface and the second backside surface.

### Claim 19 (depends on 15)

The method of claim 15, further comprising:
forming a tab recess region in one of the at least one first deep trench, wherein the tab recess region has a depth that is less than a sum of thicknesses of all layers within the first alternating layer stack and is adjoined to an upper portion of the one of the at least one first deep trench, and the first alternating layer stack is deposited in the tab recess region;
forming a contact via structure through the second substrate and on a portion of one of the at least two first metallic electrode layers within the tab recess region after bonding the second metallic bonding pads to the first metallic bonding pads.

### Claim 20 (depends on 14)

The method of claim 14, further comprising:
forming an interconnect-level dielectric layer over the second-tier capacitor assembly; and
forming contact via structures through the interconnect-level dielectric layer, wherein each of the contact via structures is electrically connected to a set of a respective one of the at least two first metallic electrode layers and a respective one of the at least two second metallic electrode layers.