# US 2023/0065535 A1 · Three-dimensional integration structure and method of forming the same

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- Number: US 2023/0065535 A1
- Document ID: US20230065535A1
- Status: Published application
- Kind: A1
- Application number: 17/451,335
- Filed: 2021-10-19
- Published: 2023-03-02
- Earliest claimed: 2021-09-02
- Assignees: Yangtze Memory Technologies Co., Ltd.
- Applicants: Yangtze Memory Technologies Co., Ltd.
- Inventors: SiPing HU
- Web page: https://patentgrep.com/patent/US20230065535A1

## CPC

- H10B 41/35: with a cell select transistor, e.g. NAND
- H10B 41/27: the channels comprising vertical portions, e.g. U-shaped channels
- H10B 41/41: of a memory region comprising a cell select transistor, e.g. NAND
- H10B 41/50: characterised by the boundary region between the core region and the peripheral circuit region
- H10B 43/27: the channels comprising vertical portions, e.g. U-shaped channels
- H10B 43/35: with cell select transistors, e.g. NAND
- H10B 43/40: characterised by the peripheral circuit region
- H10B 43/50: characterised by the boundary region between the core and peripheral circuit regions
- H10B 80/00: Assemblies of multiple devices comprising at least one memory device covered by this subclass
- H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
- H10W 80/312: {characterised by the direct bonding of electrically conductive pads}
- H10W 80/327: {characterised by the direct bonding of insulating parts, e.g. of silicon oxide layers}
- H10W 90/20: Configurations of stacked chips
- H10W 90/297: {characterised by the through-semiconductor vias [TSVs] in the stacked chips}
- H10W 90/722: {between stacked chips}
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/726: {between a chip and a stacked lead frame, conducting package substrate or heat sink}
- H10B: ELECTRONIC MEMORY DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor device is provided. The semiconductor device includes a first substrate layer having a first side over which devices are formed. In the semiconductor device, a first dielectric structure is formed over the first side of the first substrate layer in which the devices are positioned. The first dielectric structure includes a bottom surface in contact with the first side of the first substrate layer. A portion of the bottom surface of the first dielectric structure is not covered by the first substrate layer. The semiconductor device also includes a first electronic structure positioned over the uncovered portion of the bottom surface of the first dielectric structure such that the first electronic structure and the first substrate layer are positioned at a same side of the bottom surface of the first dielectric structure. The first electronic structure is bonded to the first dielectric structure.

## Claims

### Claim 1

A semiconductor device, comprising:
a first substrate layer having a first side over which devices are formed;
a first dielectric structure formed over the first side of the first substrate layer in which the devices are positioned, the first dielectric structure including a bottom surface in contact with the first side of the first substrate layer, a portion of the bottom surface of the first dielectric structure not being covered by the first substrate layer; and
a first electronic structure positioned over the uncovered portion of the bottom surface of the first dielectric structure such that the first electronic structure and the first substrate layer are positioned at a same side of the bottom surface of the first dielectric structure, the first electronic structure further being bonded to the first dielectric structure.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, wherein the first electronic structure is bonded to the bottom surface of the first dielectric structure through a polysilicon layer, the polysilicon layer being positioned between the first electronic structure and the first dielectric structure.

### Claim 3 (depends on 1)

The semiconductor device of claim 1, wherein the first electronic structure is formed from a portion of the first substrate layer.

### Claim 4 (depends on 1)

The semiconductor device of claim 1, wherein the devices include at least one of a field effect transistor, a diode, a bipolar junction transistor, a capacitor, a resistor, or an inductor.

### Claim 5 (depends on 1)

The semiconductor device of claim 1, wherein the devices include memory cells that further comprise:
a stack of alternating insulating layers and word lines that is positioned over the first side of the first substrate layer in a staircase configuration and arranged in the first dielectric structure,
a channel structure that extends through the insulating layers and the word lines, and
a word line contact that is positioned over the first side of the first substrate layer and extends from one of the word lines.

### Claim 6 (depends on 5)

The semiconductor device of claim 5, further comprising:
a first contact structure extending from the first side of the first substrate layer and extending through the first dielectric structure;
a through silicon via (TSV) formed in the first substrate layer, the TSV extending through the first substrate layer and being in contact with the first contact structure;
a first metal line formed over the first side of the first substrate layer and arranged on a top surface the first dielectric structure that is opposite to the bottom surface, the first metal line being coupled to one of the channel structure, the first contact structure, and the word line contact; and
a pad structure positioned over and coupled to the TSV.

### Claim 7 (depends on 6)

The semiconductor device of claim 6, further comprising:
a second dielectric structure formed over a first side of a second substrate layer, the first side of the first substrate layer and the first side of the second substrate layer being aligned;
a transistor formed in the first side of a second substrate layer and positioned in the second dielectric structure; and
a second metal line formed over the second dielectric structure and coupled to the first metal line such that the memory cells are coupled to the transistor.

### Claim 8 (depends on 7)

The semiconductor device of claim 7, further comprising
a source/drain (S/D) contact extending from a S/D region of the transistor;
a gate contact extending from a gate structure of the transistor; and
a second contact structure extending from the first side of the second substrate layer and extending through the second dielectric structure, wherein:
the second metal line is coupled to one of the S/D contact, the gate contact, and the second contact structure, and
the first metal line is coupled to the second metal line through a bonding via that is positioned between the first metal line and the second metal line.

### Claim 9 (depends on 1)

The semiconductor device of claim 1, wherein the first electronic structure includes one of logic circuitry, storage circuitry, and analog circuitry.

### Claim 10 (depends on 8)

The semiconductor device of claim 8, further comprising:
a second electronic structure positioned over the uncovered portion of the bottom surface of the first dielectric structure and coupled to the first electronic structure, and
a third electronic structure coupled to the transistor through the first contact structure and the second contact structure.

### Claim 11

A method for fabricating a semiconductor device, comprising:
forming devices over a first side of a first substrate layer;
forming a first dielectric structure over the first side of the first substrate layer such that the devices are positioned in the first dielectric structure, the first dielectric structure including a bottom surface in contact with the first side of the first substrate layer;
removing a portion of the first substrate layer such that a portion of the bottom surface of the first dielectric structure is not covered by the first substrate layer; and
bonding a first electronic structure to the first dielectric structure, the first electronic structure being positioned over the uncovered portion of the bottom surface of the first dielectric structure such that the first electronic structure and the first substrate layer are positioned at a same side of the bottom surface of the first dielectric structure.

### Claim 12 (depends on 11)

The method of claim 11, wherein:
the first electronic structure includes one of logic circuitry, storage circuitry, and analog circuitry, and
the devices include at least one of a field effect transistor, a diode, a bipolar junction transistor, a capacitor, a resistor, an inductor, or a memory cell.

### Claim 13 (depends on 11)

The method of claim 11, wherein the bonding the first electronic structure further comprises:
forming a polysilicon layer over the uncovered portion of the bottom surface of the first dielectric structure;
positioning the first electronic structure over the polysilicon layer; and
performing an annealing process so that the polysilicon layer connects the first electronic structure and the first dielectric structure and functions as a substrate layer for the first electronic structure.

### Claim 14 (depends on 13)

The method of claim 13, wherein the annealing process includes a laser annealing process that includes:
laser energy larger than 0.1 J/cm2,
a laser beam wavelength in a range from 350 nm to 650 nm,
a process time in a range from 10 fs to 1 us per pulse, and
one of a continuous laser annealing process and a pulsed laser annealing process.

### Claim 15 (depends on 11)

The method of claim 11, wherein the bonding the first electronic structure further comprises:
forming the first electronic structure from a portion of the first substrate layer.

### Claim 16 (depends on 11)

The method of claim 11, wherein
the forming the devices further includes forming memory cells over the first side of the first substrate layer, and
the memory cells includes:
a stack of alternating insulating layers and word lines that is positioned over the first side of the first substrate layer in a staircase configuration and arranged in the first dielectric structure,
a channel structure that extends from the first side of the first substrate layer and extends through the insulating layers and the word lines, and
a word line contact that is positioned over the first side of the first substrate layer and extends from one the word lines.

### Claim 17 (depends on 16)

The method of claim 16, further comprising:
forming a first contact structure that extends from the first side of the first substrate layer and extends through the first dielectric structure;
forming a through silicon via (TSV) in the first substrate layer, the TSV extending through the first substrate layer and being in contact with the first contact structure;
forming a first metal line over the first side of the first substrate layer and arranged on a top surface of the first dielectric structure that is opposite to the bottom surface, the first metal line being coupled to one of the channel structure, the first contact structure, and the word line contact; and
forming a pad structure positioned over and coupled to the TSV.

### Claim 18 (depends on 17)

The method of claim 17, further comprising:
forming a second dielectric structure over a first side of a second substrate layer, the first side of the first substrate layer and the first side of the second substrate layer being aligned to face each other;
forming a transistor in the first side of a second substrate layer, the transistor being positioned in the second dielectric structure; and
forming a second metal line over the second dielectric structure, the second metal line being coupled to the first metal line so that the memory cells are coupled to the transistor.

### Claim 19 (depends on 18)

The method of claim 18, further comprising
forming a source/drain (S/D) contact that extends from a S/D region of the transistor;
forming a gate contact that extends from a gate structure of the transistor; and
forming a second contact structure that extends from the first side of the second substrate layer and extends through the second dielectric structure, wherein:
the second metal line is coupled to one of the S/D contact, the gate contact, and the second contact structure, and
the first metal line is coupled to the second metal line through a bonding via that is positioned between the first metal line and the second metal line.

### Claim 20 (depends on 19)

The method of claim 19, further comprises:
forming a second electronic structure over the uncovered portion of the bottom surface of the first dielectric structure, the second electronic structure being coupled to the first electronic structure, and
forming a third electronic structure over the uncovered portion of the bottom surface of the first dielectric structure that is coupled to the transistor through the first contact structure and the second contact structure.