# US 2023/0058451 A1 · Lateral bipolar transistor structure with marker layer for emitter and collector > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2023/0058451 A1 - Document ID: US20230058451A1 - Status: Published application - Kind: A1 - Application number: 17/450,842 - Filed: 2021-10-14 - Published: 2023-02-23 - Earliest claimed: 2021-08-23 - Assignees: GlobalFoundries U.S. Inc. - Applicants: GlobalFoundries U.S. Inc. - Inventors: Vibhor Jain; Alexander M. Derrickson; Judson R. Holt - Web page: https://patentgrep.com/patent/US20230058451A1 ## CPC - H10D 10/60: Lateral BJTs - H10D 10/061: {of lateral BJTs (of heterojunction BJTs H10D10/021; of thin film BJTs H10D10/041)} - H10D 10/311: {Thin-film BJTs} - H10D 62/115: {Dielectric isolations, e.g. air gaps} - H10D 62/134: {of lateral BJTs} - H10D 62/137: {Collector regions of BJTs} - H10D 86/201: {the substrates comprising an insulating layer on a semiconductor body, e.g. SOI (H10D86/40 take precedence)} - H10D 10/80: Heterojunction BJTs - H10D 62/184: {of lateral BJTs} - H10D 64/231: {Emitter or collector electrodes for bipolar transistors} - H10D 84/401: {Combinations of FETs or IGBTs with BJTs} - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES ## Abstract Embodiments of the disclosure provide a lateral bipolar transistor structure with a marker layer for emitter and collector terminals. A lateral bipolar transistor structure according to the disclosure includes a semiconductor layer over an insulator layer. The semiconductor layer includes an emitter/collector (E/C) region having a first doping type and an intrinsic base region adjacent the E/C region and having a second doping type opposite the first doping type. A marker layer is on the E/C region of the semiconductor layer, and a raised E/C terminal is on the marker layer. An extrinsic base is on the intrinsic base region of the semiconductor layer, and a spacer is horizontally between the raised E/C terminal and the extrinsic base. ## Claims ### Claim 1 A lateral bipolar transistor structure comprising: a semiconductor layer over an insulator layer, the semiconductor layer including: an emitter/collector (E/C) region having a first doping type, and an intrinsic base region adjacent the E/C region and having a second doping type opposite the first doping type; a marker layer on the E/C region of the semiconductor layer; a raised E/C terminal on the marker layer; an extrinsic base on the intrinsic base region of the semiconductor layer; and a spacer horizontally between the raised E/C terminal and the extrinsic base. ### Claim 2 (depends on 1) The lateral bipolar transistor structure of claim 1, wherein a material composition of the marker layer is configured for etch selectivity to the raised E/C terminal and the E/C region. ### Claim 3 (depends on 2) The lateral bipolar transistor structure of claim 2, wherein the material composition of the marker layer includes silicon germanium (SiGe). ### Claim 4 (depends on 3) The lateral bipolar transistor structure of claim 3, wherein the intrinsic base region includes SiGe, and wherein a germanium concentration of the intrinsic base region is greater than a germanium concentration of the marker layer. ### Claim 5 (depends on 1) The lateral bipolar transistor structure of claim 1, wherein the semiconductor layer includes a semiconductor on insulator (SOI) layer on a buried insulator layer and adjacent a trench isolation (TI). ### Claim 6 (depends on 1) The lateral bipolar transistor structure of claim 1, wherein the marker layer is above a semiconductor on insulator (SOI) layer, and wherein a lower surface of the marker layer is on a portion of the SOI layer and a portion of a trench isolation (TI) adjacent the SOI layer. ### Claim 7 (depends on 1) The lateral bipolar transistor structure of claim 1, wherein the spacer includes an oxide layer horizontally adjacent a nitride layer. ### Claim 8 A lateral bipolar transistor structure comprising: a semiconductor on insulator (SOI) layer on a buried insulator layer and adjacent a trench isolation (TI); a semiconductor stack on a first portion of the SOI layer, the semiconductor stack including a first marker layer, a doped semiconductor layer on the first marker layer, and a second marker layer on the doped semiconductor layer; a raised E/C terminal on the semiconductor stack; a base terminal on a second portion of the SOI layer, the base terminal including an intrinsic base region on the SOI layer and an extrinsic base region on the intrinsic base region; and a spacer horizontally between the raised E/C terminal and the extrinsic base region of the base terminal. ### Claim 9 (depends on 8) The lateral bipolar transistor structure of claim 8, wherein a material composition of the marker layer is configured for etch selectivity to the raised E/C terminal and the SOI layer. ### Claim 10 (depends on 8) The lateral bipolar transistor structure of claim 8, wherein a vertical thickness of the SOI layer is less than a vertical thickness of the doped semiconductor layer of the semiconductor stack. ### Claim 11 (depends on 8) The lateral bipolar transistor structure of claim 8, wherein a horizontal interface between the semiconductor stack and the intrinsic base region of the base terminal is below the spacer. ### Claim 12 (depends on 8) The lateral bipolar transistor structure of claim 8, wherein a portion of the semiconductor stack is over the TI. ### Claim 13 (depends on 8) The lateral bipolar transistor structure of claim 8, wherein a vertical thickness of the E/C terminal is approximately equal to a vertical thickness of the extrinsic base region of the base terminal. ### Claim 14 (depends on 8) The lateral bipolar transistor structure of claim 8, wherein the spacer includes an oxide layer horizontally adjacent a nitride layer. ### Claim 15 A method of forming a lateral bipolar transistor structure, the method comprising: forming an emitter/collector (E/C) region having a first doping type in a first portion of a semiconductor layer; forming an intrinsic base region in a second portion of the semiconductor layer adjacent the E/C region, the intrinsic base region having a second doping type opposite the first doping type; forming a marker layer on the E/C region of the semiconductor layer; forming a raised E/C terminal over the marker layer; forming an extrinsic base on the intrinsic base region of the semiconductor layer; and forming a spacer horizontally between the raised E/C terminal and the extrinsic base. ### Claim 16 (depends on 15) The method of claim 15, wherein forming the marker layer further includes forming a portion of the marker layer on a trench isolation (TI) region adjacent the semiconductor layer. ### Claim 17 (depends on 15) The method of claim 15, wherein forming the intrinsic base region includes forming a semiconductor having the second doping type within an opening of the second portion of the semiconductor layer, the opening having a lower surface that is above a lower surface of the semiconductor layer. ### Claim 18 (depends on 15) The method of claim 15, further comprising forming the semiconductor layer above a semiconductor on insulator (SOI) layer, wherein the first portion of the semiconductor layer is above a portion of the SOI layer and a trench isolation (TI) adjacent the SOI layer. ### Claim 19 (depends on 15) The method of claim 15, further comprising: forming a doped semiconductor layer on the marker layer; and forming an additional marker layer on the doped semiconductor layer, wherein forming the raised E/C terminal includes forming the raised E/C terminal on the additional marker layer. ### Claim 20 (depends on 15) The method of claim 15, wherein forming the spacer includes: forming an oxide layer on a sidewall of the raised E/C terminal; and forming a nitride layer on a sidewall of the oxide layer opposite the raised E/C terminal.