# US 2023/0058221 A1 · Gate structures in semiconductor devices

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- Number: US 2023/0058221 A1
- Document ID: US20230058221A1
- Status: Published application
- Kind: A1
- Application number: 17/406,874
- Filed: 2021-08-19
- Published: 2023-02-23
- Earliest claimed: 2021-08-19
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Co., Ltd.
- Inventors: Hsiang-Pi CHANG; Chung-Liang Cheng; I-Ming Chang; Yao-Sheng Huang; Huang-Lin Chao
- Web page: https://patentgrep.com/patent/US20230058221A1

## CPC

- H10P 32/20: Diffusion for doping of insulating layers
- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 30/62: Fin field-effect transistors [FinFET]
- H10D 30/6211: {having fin-shaped semiconductor bodies integral with the bulk semiconductor substrates}
- H10D 64/0134: {with a treatment, e.g. annealing, after the formation of the insulator and before the formation of the conductor}
- H10D 64/691: {comprising metallic compounds, e.g. metal oxides or metal silicates (insulators comprising nitrogen H10D64/693)}
- H10D 84/0158: {the components including FinFETs}
- H10D 84/0181: {Manufacturing their gate insulating layers}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/8314: {the IGFETs characterised by having gate insulating layers with different properties}
- H10D 84/853: {comprising FinFETs}
- H10P 14/69396: {the material containing at least one rare earth metal element, e.g. oxides of lanthanides, scandium or yttrium}
- H10P 95/90: Thermal treatments, e.g. annealing or sintering
- H10D 84/83135: {the IGFETs characterised by having different gate conductor materials or different gate conductor implants}
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A semiconductor device with different configurations of gate structures and a method of fabricating the same are disclosed. The method includes forming a fin structure on a substrate, forming a gate opening on the fin structure, forming a metallic oxide layer within the gate opening, forming a first dielectric layer on the metallic oxide layer, forming a second dielectric layer on the first dielectric layer, forming a work function metal (WFM) layer on the second dielectric layer, and forming a gate metal fill layer on the WFM layer. The forming the first dielectric layer includes depositing an oxide material with an oxygen areal density less than an oxygen areal density of the metallic oxide layer.

## Claims

### Claim 1

A method, comprising:
forming a fin structure on a substrate;
forming a gate opening on the fin structure;
forming a metallic oxide layer within the gate opening;
forming a first dielectric layer on the metallic oxide layer, wherein the forming the first dielectric layer comprises depositing an oxide material with an oxygen areal density less than an oxygen areal density of the metallic oxide layer;
forming a second dielectric layer on the first dielectric layer;
forming a work function metal (WFM) layer on the second dielectric layer; and
forming a gate metal fill layer on the WFM layer.

### Claim 2 (depends on 1)

The method of claim 1, wherein the forming the metallic oxide layer comprises depositing an oxide of a metallic material with an electronegativity value greater than an electronegativity value of a metal or a semiconductor of the first dielectric layer.

### Claim 3 (depends on 1)

The method of claim 1, wherein the forming the metallic oxide layer comprises depositing an oxide of a metallic material that is different from a metallic material of the second dielectric layer.

### Claim 4 (depends on 1)

The method of claim 1, further comprising forming an interfacial oxide layer on the fin structure.

### Claim 5 (depends on 4)

The method of claim 4, wherein the forming the metallic oxide layer comprises depositing the metallic oxide layer on the interfacial oxide layer.

### Claim 6 (depends on 1)

The method of claim 1, wherein the forming the metallic oxide layer comprises depositing an oxide of gallium, aluminum, or indium.

### Claim 7 (depends on 1)

The method of claim 1, wherein the forming the second dielectric layer comprises depositing the second dielectric layer with a thickness greater than a thickness of the first dielectric layer.

### Claim 8

A method, comprising:
forming first and second fin structures on a substrate;
forming first and second gate openings on the first and second fin structures, respectively;
forming a first dielectric layer with first and second layer portions formed within the first and second gate openings, respectively;
selectively doping the first layer portion with first dopants, wherein the first dopants have an electronegativity value greater than an electronegativity value of a metal or a semiconductor of the first dielectric layer;
selectively doping the second layer portion with second dopants different from the first dopants, wherein the second dopants have an electronegativity value less than an electronegativity value of the metal or the semiconductor of the first dielectric layer;
forming a second dielectric layer with first and second layer portions on the first and second layer portions of the first dielectric layer; and
forming first and second gate metal fill layers over the first and second layer portions of the second dielectric layer, respectively.

### Claim 9 (depends on 8)

The method of claim 8, wherein the selectively doping the first layer portion with the first dopants comprises:
forming a metallic oxide layer on the first and second layer portions of the first dielectric layer;
removing a portion of the metallic oxide layer on the second layer portion of the first dielectric layer; and
performing an annealing process.

### Claim 10 (depends on 9)

The method of claim 9, wherein the forming the metallic oxide layer comprises depositing an oxide material with an oxygen areal density greater than an oxygen areal density of an oxide material of the first dielectric layer.

### Claim 11 (depends on 9)

The method of claim 9, wherein the forming the metallic oxide layer comprises depositing an oxide of gallium, aluminum, or indium.

### Claim 12 (depends on 8)

The method of claim 8, wherein the selectively doping the second layer portion with the second dopants comprises:
forming a rare-earth metal oxide layer on the first and second layer portions of the first dielectric layer;
removing a portion of the rare-earth metal oxide layer on the first layer portion of the first dielectric layer; and
performing an annealing process.

### Claim 13 (depends on 12)

The method of claim 12, wherein the forming the rare-earth metal oxide layer comprises depositing an oxide material with an oxygen areal density less than an oxygen areal density of an oxide material of the first dielectric layer.

### Claim 14 (depends on 8)

The method of claim 8, further comprising:
selectively forming a p-type work function metal (pWFM) layer on the first layer portion of the second dielectric layer; and
selectively forming an n-type work function metal (nWFM) layer on the second layer portion of the second dielectric layer.

### Claim 15 (depends on 8)

The method of claim 8, wherein the forming the second dielectric layer comprises depositing the second dielectric layer with a thickness greater than a thickness of the first dielectric layer.

### Claim 16

A semiconductor device, comprising:
a substrate;
a fin structure disposed on the substrate;
a semiconductor oxide layer disposed on the fin structure;
a metallic oxide layer disposed on the semiconductor oxide layer;
a first dielectric layer disposed on the metallic oxide layer, wherein a metallic material of the metallic oxide layer has an electronegativity value greater than an electronegativity value of a metal or a semiconductor the first dielectric layer;
a second dielectric layer disposed on the first dielectric layer;
a work function metal (WFM) layer disposed on the second dielectric layer; and
a gate metal fill layer on the WFM layer.

### Claim 17 (depends on 16)

The semiconductor device of claim 16, further comprising a dipole layer disposed at an interface between the metallic oxide layer and the semiconductor oxide layer.

### Claim 18 (depends on 17)

The semiconductor device of claim 17, wherein the dipole layer comprises a metallic atom of the metallic oxide layer and an oxygen atom of the semiconductor oxide layer.

### Claim 19 (depends on 16)

The semiconductor device of claim 16, wherein the second dielectric layer has a thickness greater than a thickness of the first dielectric layer.

### Claim 20 (depends on 16)

The semiconductor device of claim 16, wherein an oxygen areal density of the metallic oxide layer is greater than an oxygen areal density of the first dielectric layer.