# US 2023/0058077 A1 · Adc circuitry comprising compensation circuitry > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2023/0058077 A1 - Document ID: US20230058077A1 - Status: Published application - Kind: A1 - Application number: 17/880,417 - Filed: 2022-08-03 - Published: 2023-02-23 - Earliest claimed: 2021-08-23 - Assignees: Socionext Inc. - Applicants: Socionext Inc. - Inventors: Sandeep SANTHOSH KUMAR; Jayaraman KUMAR; Armin JALILI SEBARDAN; Martin WILSON - Web page: https://patentgrep.com/patent/US20230058077A1 ## CPC - H03M 1/0604: {at one point, i.e. by adjusting a single reference value, e.g. bias or gain error (gain setting for range control H03M1/18)} - H03M 1/403: {using switched capacitors} - H03M 1/0678: {using additional components or elements, e.g. dummy components} - H03M 1/0863: {of switching transients, e.g. glitches} - H03M 1/468: {in which the input S/H circuit is merged with the feedback DAC array} - H03M 1/804: {with charge redistribution} - H03M: CODING; DECODING; CODE CONVERSION IN GENERAL (using fluidic means F15C4/00; optical analogue/digital converters G02F7/00; coding, decoding or code conversion, specially adapted for particular applications, see the relevant subclasses, e.g. G01D, G01R, G06F, G06T, G09G, G10L, G11B, G11C, H04B, H04L, H04M, H04N; ciphering or deciphering for cryptography or other purposes involving the need for secrecy G09C) ## Abstract Analogue-to-digital converter, ADC, circuitry comprising: successive-approximation circuitry configured in a subconversion operation to draw a charge from a first voltage reference, REF1; compensation circuitry comprising at least one compensation capacitor and configured, in a precharge operation prior to the subconversion operation, to connect the at least one compensation capacitor so that the at least one compensation capacitor stores a compensation charge, and, in the subconversion operation, to connect the at least one compensation capacitor to the first voltage reference so that a charge is injected into the first voltage reference, REF1; and control circuitry, wherein: the successive-approximation circuitry and the compensation circuitry are configured such that one or more parameters defining at least one of said charges are controllable; and the control circuitry is configured to adjust at least one said parameter to adjust an extent to which the charge injected into the first voltage reference, REF1, by the compensation circuitry compensates for the charge drawn from the first voltage reference, REF1, by the successive-approximation circuitry. ## Claims ### Claim 1 Analogue-to-digital converter, ADC, circuitry comprising: successive-approximation circuitry configured in a subconversion operation to draw a charge from a first voltage reference, REF1; compensation circuitry comprising at least one compensation capacitor and configured, in a precharge operation prior to the subconversion operation, to connect the at least one compensation capacitor so that the at least one compensation capacitor stores a compensation charge, and, in the subconversion operation, to connect the at least one compensation capacitor to the first voltage reference so that a charge is injected into the first voltage reference, REF1; and control circuitry, wherein: the successive-approximation circuitry and the compensation circuitry are configured such that one or more parameters defining at least one of said charges are controllable; and the control circuitry is configured to adjust at least one said parameter to adjust an extent to which the charge injected into the first voltage reference, REF1, by the compensation circuitry compensates for the charge drawn from the first voltage reference, REF1, by the successive-approximation circuitry. ### Claim 2 (depends on 1) The ADC circuitry as claimed in claim 1, wherein the control circuitry is configured to adjust the at least one said parameter based on a measure of settling time of the first voltage reference, optionally of settling time of the first voltage reference responsive to one or more previous subconversion operations. ### Claim 3 (depends on 1) The ADC circuitry as claimed in claim 1, wherein the one or more parameters comprise at least one of: a voltage level of at least one REF node to which the at least one compensation capacitor is connected in the subconversion operation; a capacitance of at least one capacitor of the successive-approximation circuitry; a voltage level of at least one voltage-reference node to which the at least one compensation capacitor is connected in the precharge operation; and a capacitance of the at least one compensation capacitor. ### Claim 4 (depends on 1) The ADC circuitry as claimed in claim 1, wherein: the successive-approximation circuitry comprises an array of capacitors and is configured in the subconversion operation to switch at least one of the array of capacitors between different REF nodes of the first voltage reference, REF1, having different defined voltage levels such that a first charge is drawn from a first REF1 node and a second charge is injected into a second REF1 node; the compensation circuitry is configured, in the subconversion operation, to connect the at least one compensation capacitor between the first and second REF nodes so that a third charge is injected into the first REF1 node and a fourth charge is drawn from the second REF1 node; and the control circuitry is configured to adjust the at least one said parameter to adjust an extent to which the third and fourth charges compensate for the first and second charges, respectively. ### Claim 5 (depends on 4) The ADC circuitry as claimed in claim 4, wherein the compensation circuitry is configured, in the precharge operation, to connect the at least one compensation capacitor between different REF2 nodes of a second voltage reference, REF2, having different defined voltage levels so that the at least one compensation capacitor stores the compensation charge. ### Claim 6 (depends on 5) The ADC circuitry as claimed in claim 5, wherein the compensation circuitry is configured, in the subconversion operation, to disconnect the at least one compensation capacitor from at least a first REF2 node to which the at least one compensation capacitor is connected in the precharge operation. ### Claim 7 (depends on 6) The ADC circuitry as claimed in claim 6, wherein the first voltage reference is configured to regulate the voltage level of at least the first REF node and/or the second voltage reference is configured to regulate the voltage level of at least the first REF2 node. ### Claim 8 (depends on 6) The ADC circuitry as claimed in claim 6, wherein: the first voltage reference is configured to regulate the voltage level of the first REF node and the voltage level of the second REF node, optionally relative to a voltage level of a shared reference node, such as a ground node; and the second voltage reference is configured to regulate the voltage level of the first REF2 node and the voltage level of a second REF2 node to which the at least one compensation capacitor is connected in the precharge operation, optionally relative to a voltage level of the shared reference node or another shared reference node, such as a ground node. ### Claim 9 (depends on 8) The ADC circuitry as claimed in claim 8, wherein the compensation circuitry is configured, in the subconversion operation, to disconnect the at least one compensation capacitor from the first and second REF2 nodes and connect the at least one compensation capacitor between the first and second REF nodes. ### Claim 10 (depends on 4) The ADC circuitry as claimed in claim 4, wherein the compensation circuitry is configured such that the at least one compensation capacitor is disconnected from the first and second REF nodes in the precharge operation. ### Claim 11 (depends on 1) The ADC circuitry as claimed in claim 1, wherein: said subconversion operation is a first subconversion operation, said at least one compensation capacitor is at least one first compensation capacitor, said precharge operation is a first precharge operation, and said compensation charge is a first compensation charge; the successive-approximation circuitry is configured in a second subconversion operation to draw a charge from the first voltage reference, REF1; the compensation circuitry comprises at least one second compensation capacitor and is configured, in a second precharge operation prior to the second subconversion operation, to connect the at least one second compensation capacitor so that the at least one second compensation capacitor stores a second compensation charge, and, in the second subconversion operation, to connect the at least one second compensation capacitor to the first voltage reference so that a charge is injected into the first voltage reference, REF1; and the successive-approximation circuitry and the compensation circuitry are configured such that one or more parameters defining at least one of said charges are controllable, optionally wherein the control circuitry is configured to adjust at least one said parameter to adjust an extent to which the charge injected into the first voltage reference, REF1, by the compensation circuitry in the second subconversion operation compensates for the charge drawn from the first voltage reference, REF1, by the successive-approximation circuitry in the second subconversion operation, optionally wherein the compensation circuitry is configured, in the second precharge operation, to connect the at least one second compensation capacitor between different REF3 nodes of a third voltage reference, REF3, having different defined voltage levels so that the at least one second compensation capacitor stores the second compensation charge. ### Claim 12 Analogue-to-digital converter, ADC, circuitry comprising: successive-approximation circuitry configured in a subconversion operation to draw a charge from a first voltage reference, REF1; and compensation circuitry comprising at least one compensation capacitor and configured, in a precharge operation prior to the subconversion operation, to connect the at least one compensation capacitor between nodes of a second voltage reference, REF2, so that the at least one compensation capacitor stores a compensation charge, and, in the subconversion operation, to disconnect the at least one compensation capacitor from at least one of said nodes of the second voltage reference, REF2, whose voltage is regulated by the second voltage reference, REF2, and connect the at least one compensation capacitor between nodes of the first voltage reference, REF1, so that a charge is injected into the first voltage reference, REF1. ### Claim 13 (depends on 12) The ADC circuitry as claimed in claim 12, wherein: the second voltage reference, REF2, comprises a plurality of REF2 nodes having different defined voltage levels, the plurality of REF2 nodes comprising a first REF2 node and a second REF2 node, the second voltage reference configured to regulate the voltage level of the first REF2 node relative to the voltage level of the second REF2 node or to regulate the voltage level of the first REF2 node and the voltage level of the second REF2 node relative to a voltage level of a first shared reference node; and the compensation circuitry is configured, in the precharge operation, to connect the at least one compensation capacitor between the first and second REF2 nodes so that the at least one compensation capacitor stores the compensation charge, and, in the subconversion operation, to disconnect the at least one compensation capacitor from at least the first REF2 node. ### Claim 14 (depends on 13) The ADC circuitry as claimed in claim 13, wherein: the second voltage reference is configured to regulate the voltage level of the first REF2 node and the voltage level of the second REF2 node relative to the voltage level of the first shared reference node; and the compensation circuitry is configured, in the subconversion operation, to disconnect the at least one compensation capacitor from the first and second REF2 nodes. ### Claim 15 (depends on 1) Integrated circuitry, such as an IC chip, comprising the ADC circuitry of claim 1.