# US 2023/0057562 A1 · Managing inter-processor interrupts in virtualized computer systems > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2023/0057562 A1 - Document ID: US20230057562A1 - Status: Published application - Kind: A1 - Application number: 17/404,947 - Filed: 2021-08-17 - Published: 2023-02-23 - Earliest claimed: 2021-08-17 - Assignees: Red Hat, Inc. - Applicants: Red Hat, Inc. - Inventors: Amnon IIan; Michael Tsirkin - Web page: https://patentgrep.com/patent/US20230057562A1 ## CPC - G06F 13/24: using interrupt (G06F13/32 takes precedence) - G06F 9/45558: {Hypervisor-specific management and integration aspects} - G06F 9/5016: {the resource being the memory} - G06F 13/4221: {being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus} - G06F 2009/45579: {I/O management, e.g. providing access to device drivers or storage} - G06F 2009/45583: {Memory management, e.g. access or allocation} - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract An example method may include allocating, on a host computer system, a memory page in a memory of an input/output (I/O) device, mapping the memory page into a memory space of a virtual machine associated with a first virtual processor, creating a first entry in an interrupt mapping table in the memory of the I/O device, where the first entry includes a memory address that is associated with a second virtual processor identifier and further includes an interrupt vector identifier; and creating a second entry in an interrupt injection table of an interrupt injection unit of the host computer system, where the second entry is associated with a memory address that corresponds to a second virtual processor, the second entry includes the interrupt vector identifier, and the second entry is further associated with the second virtual processor identifier. ## Claims ### Claim 1 A method comprising: allocating, by a hypervisor running on a host computer system, a memory page in a memory of an input/output (I/O) device; mapping, by the hypervisor, the memory page into a memory space of a virtual machine associated with a first virtual processor; creating a first entry in an interrupt mapping table in the memory of the I/O device, wherein the first entry includes a memory address that is associated with a second virtual processor identifier and further includes an interrupt vector identifier; and creating a second entry in an interrupt injection table of an interrupt injection unit of the host computer system, wherein the second entry is associated with a memory address that corresponds to a second virtual processor, the second entry includes the interrupt vector identifier, and the second entry is further associated with the second virtual processor identifier. ### Claim 2 (depends on 1) The method of claim 1, wherein the I/O device communicates with the interrupt injection unit via a peripheral interface bus. ### Claim 3 (depends on 1) The method of claim 1, wherein the I/O device comprises a Peripheral Component Interconnect (PCI) card. ### Claim 4 (depends on 1) The method of claim 1, wherein creating the first entry in the interrupt mapping table in the memory of the I/O device causes the I/O device to, responsive to a write of interrupt data to the memory page, generate a message-signaled interrupt. ### Claim 5 (depends on 4) The method of claim 4, wherein the interrupt mapping table comprises a Message-Signaled Interrupt (MSI) table, and the interrupt injection unit comprises an Input-Output Memory Management Unit (IOMMU). ### Claim 6 (depends on 4) The method of claim 4, wherein creating the second entry in the interrupt injection table of the interrupt injection unit causes the interrupt injection unit to, responsive to receiving the message-signaled interrupt, generate a posted interrupt. ### Claim 7 (depends on 1) The method of claim 1, further comprising: receiving, by the virtual machine associated with the first virtual processor, a request to send an inter-processor interrupt (IPI) to the second virtual processor, wherein the IPI comprises an interrupt vector identifier, and the second virtual processor corresponds to the second virtual processor identifier; and storing the interrupt vector identifier and the second virtual processor identifier in the memory space of the virtual machine that is mapped to the memory page of the I/O device. ### Claim 8 (depends on 7) The method of claim 7, further comprising: detecting, by the I/O device, the interrupt vector identifier and the second virtual processor identifier stored in the memory page; identifying, by the I/O device, an entry in the interrupt mapping table, wherein the identified entry comprises the interrupt vector identifier and the second virtual processor identifier; and sending, by the I/O device, a message-signaled interrupt in view of the identified entry in the interrupt mapping table, wherein the message-signaled interrupt includes the interrupt vector identifier and the second virtual processor identifier. ### Claim 9 (depends on 1) The method of claim 1, further comprising: receiving, by the interrupt injection unit, a message-signaled interrupt; identifying, by the interrupt injection unit, the interrupt vector identifier and the second virtual processor identifier included in the message-signaled interrupt; and responsive to determining that the second virtual processor identified by the second virtual processor identifier is running, generating, by the interrupt injection unit, a posted interrupt at a logical processor that corresponds to the second virtual processor identifier, wherein the posted interrupt comprises the interrupt vector identifier. ### Claim 10 (depends on 9) The method of claim 9, further comprising: responsive to determining that the second virtual processor identified by the second virtual processor identifier is not running, generating, by the interrupt injection unit, a host interrupt in the host computer system, wherein the host interrupt comprises the interrupt vector identifier and is associated with the second virtual processor identifier. ### Claim 11 (depends on 10) The method of claim 10, further comprising: responsive to determining, subsequent to generating the host interrupt, that the second virtual processor is running, generating, by the interrupt injection unit, the posted interrupt at the logical processor that corresponds to the second virtual processor identifier. ### Claim 12 (depends on 9) The method of claim 9, further comprising: invoking, by the logical processor that corresponds to the second virtual processor identifier, an interrupt handler, wherein the interrupt vector identifier is provided to the interrupt handler. ### Claim 13 A system comprising: a memory; and a processing device communicably coupled to the memory, the processing device to: allocate, by a hypervisor running on a host computer system, a memory page in a memory of an input/output (I/O) device; map, by the hypervisor, the memory page into a memory space of a virtual machine associated with a first virtual processor; create a first entry in an interrupt mapping table in the memory of the I/O device, wherein the first entry includes a memory address that is associated with a second virtual processor identifier and further includes an interrupt vector identifier; and create a second entry in an interrupt injection table of an interrupt injection unit of the host computer system, wherein the second entry is associated with a memory address that corresponds to a second virtual processor, the second entry includes the interrupt vector identifier, and the second entry is further associated with the second virtual processor identifier. ### Claim 14 (depends on 13) The system of claim 13, wherein the I/O device communicates with the interrupt injection unit via a peripheral interface bus. ### Claim 15 (depends on 13) The system of claim 13, wherein the I/O device comprises a Peripheral Component Interconnect (PCI) card. ### Claim 16 (depends on 13) The system of claim 13, wherein creating the first entry in the interrupt mapping table in the memory of the I/O device causes the I/O device to, responsive to a write of interrupt data to the memory page, generate a message-signaled interrupt. ### Claim 17 A non-transitory machine-readable storage medium storing instructions that cause a processing device to: allocate, by a hypervisor running on a host computer system, a memory page in a memory of an input/output (I/O) device; map, by the hypervisor, the memory page into a memory space of a virtual machine associated with a first virtual processor; create a first entry in an interrupt mapping table in the memory of the I/O device, wherein the first entry includes a memory address that is associated with a second virtual processor identifier and further includes an interrupt vector identifier; and create a second entry in an interrupt injection table of an interrupt injection unit of the host computer system, wherein the second entry is associated with a memory address that corresponds to a second virtual processor, the second entry includes the interrupt vector identifier, and the second entry is further associated with the second virtual processor identifier. ### Claim 18 (depends on 17) The non-transitory machine-readable storage medium of claim 17, wherein the I/O device communicates with the interrupt injection unit via a peripheral interface bus. ### Claim 19 (depends on 17) The non-transitory machine-readable storage medium of claim 17, wherein the I/O device comprises a Peripheral Component Interconnect (PCI) card. ### Claim 20 (depends on 17) The non-transitory machine-readable storage medium of claim 17, wherein creating the first entry in the interrupt mapping table in the memory of the I/O device causes the I/O device to, responsive to a write of interrupt data to the memory page, generate a message-signaled interrupt.