# US 2023/0057560 A1 · Semiconductor device including re-distribution pads disposed at different levels and a method of manufacturing the same

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- Number: US 2023/0057560 A1
- Document ID: US20230057560A1
- Status: Published application
- Kind: A1
- Application number: 17/572,033
- Filed: 2022-01-10
- Published: 2023-02-23
- Earliest claimed: 2021-08-20
- Assignees: SK hynix Inc.
- Applicants: SK hynix Inc.
- Inventors: Jun Yong SONG; Kang Hun KIM; Si Yun KIM
- Web page: https://patentgrep.com/patent/US20230057560A1

## CPC

- H10W 72/90: Bond pads, in general
- H10W 72/019: {of bond pads}
- H10W 72/20: Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
- H10W 72/50: Bond wires
- H10W 70/05: of insulating or insulated package substrates, or of interposers, or of redistribution layers (manufacture or treatment of leadframes H10W70/04)
- H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40)
- H10W 70/652: Cross-sectional shapes
- H10W 70/654: Top-view layouts
- H10W 70/655: Fan-out layouts
- H10W 70/66: Conductive materials thereof
- H10W 70/68: Shapes or dispositions thereof
- H10W 72/01935: {by plating, e.g. electroless plating or electroplating}
- H10W 72/01953: {by etching}
- H10W 72/01955: {by using masks}
- H10W 72/07554: {changes in dispositions}
- H10W 72/222: {Multilayered bumps, e.g. a coating on top and side surfaces of a bump core}
- H10W 72/227: {Multiple bumps having different sizes}
- H10W 72/252: {comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu}
- H10W 72/547: {Dispositions of multiple bond wires}
- H10W 72/922: {Bond pads being integral with underlying chip-level interconnections}
- H10W 72/9223: {with redistribution layers [RDL]}
- H10W 72/923: {Bond pads having multiple stacked layers}
- H10W 72/944: {Dispositions of multiple bond pads}
- H10W 72/952: {comprising metals or metalloids, e.g. PbSn, Ag or Cu}
- H10W 74/147: {the encapsulations being multilayered}
- H10W 90/754: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor device includes a chip body; a passivation layer on the chip body; a lower dielectric layer on the passivation layer; a first re-distribution pad on the lower dielectric layer; an upper dielectric layer on the lower dielectric layer, the upper dielectric layer having a groove that exposes an upper surface of the first re-distribution pad; and a second re-distribution pad on the upper dielectric layer. An upper surface of the second re-distribution pad is positioned at a higher level than the upper surface of the first re-distribution pad.

## Claims

### Claim 1

A semiconductor device, comprising:
a chip body;
a passivation layer on the chip body;
a lower dielectric layer on the passivation layer;
a first re-distribution pad disposed on the lower dielectric layer;
an upper dielectric layer on the lower dielectric layer, the upper dielectric layer having a groove that exposes an upper surface of the first re-distribution pad; and
a second re-distribution pad on the upper dielectric layer,
wherein an upper surface of the second re-distribution pad is positioned at a higher level than the upper surface of the first re-distribution pad.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, wherein the chip body further includes:
a first metal pad disposed in a first region; and
a second metal pad disposed in a second region,
wherein the passivation layer exposes an upper surface of the first metal pad and an upper surface of the second metal pad.

### Claim 3 (depends on 2)

The semiconductor device of claim 2, wherein the first re-distribution pad includes:
a first via portion penetrating the lower dielectric layer to be coupled with the first metal pad;
a first extended portion disposed on the lower dielectric layer to extend from the first via portion in a first horizontal direction; and
a first pad portion corresponding to an end portion of the first extended portion,
wherein:
the first via portion is disposed near a center of the chip body, and
the first pad portion is disposed near an edge of the chip body.

### Claim 4 (depends on 3)

The semiconductor device of claim 3, wherein the second re-distribution pad includes:
a second via portion penetrating the upper dielectric layer and the lower dielectric layer to be coupled with the second metal pad;
a second extended portion disposed on the upper dielectric layer to extend from the second via portion in the first horizontal direction; and
a second pad portion corresponding to an end portion of the second extended portion, and
wherein:
the second via portion is disposed near the center of the chip body, and
the second pad portion is disposed near the edge of the chip body.

### Claim 5 (depends on 4)

The semiconductor device of claim 4, further comprising:
a first metal liner conformally formed on a lower surface of the first re-distribution pad; and
a second metal liner conformally formed on a lower surface of the second re-distribution pad.

### Claim 6 (depends on 1)

The semiconductor device of claim 1, further comprising:
a protective dielectric layer that covers the first re-distribution pad and the second re-distribution pad,
wherein the protective dielectric layer includes a first connection hole that exposes a portion of the first re-distribution pad and includes a second connection hole that exposes a portion of the second re-distribution pad.

### Claim 7 (depends on 6)

The semiconductor device of claim 6, further comprising:
a first pillar disposed in the first connection hole; and
a second pillar disposed in the second connection hole.

### Claim 8 (depends on 7)

The semiconductor device of claim 7, wherein an upper end of the first pillar and an upper end of the second pillar are positioned at a same level.

### Claim 9

A semiconductor device, comprising:
a chip body having a first metal pad and a second metal pad;
a passivation layer on the chip body;
a lower dielectric layer on the passivation layer;
a first re-distribution pad on the lower dielectric layer;
an upper dielectric layer on the lower dielectric layer, the upper dielectric layer having a groove that exposes an upper surface of the first re-distribution pad; and
a second re-distribution pad on the upper dielectric layer,
wherein the first re-distribution pad includes:
a first via portion vertically penetrating the lower dielectric layer to be coupled with the first metal pad; and
a first extended portion extending from the first via portion in a first horizontal direction, and
wherein the second re-distribution layer includes:
a second via portion vertically penetrating the upper dielectric layer and the lower dielectric layer to be coupled with the second metal pad; and
a second extended portion extending from the second via portion in the first horizontal direction.

### Claim 10

A semiconductor device, comprising:
a lower dielectric layer disposed on a chip body;
a plurality of first re-distribution pads disposed on the lower dielectric layer;
an upper dielectric layer disposed on the lower dielectric layer, the upper dielectric layer having grooves that expose the first re-distribution pads; and
a plurality of second re-distribution pads disposed on the upper dielectric layer,
wherein:
the first re-distribution pads and the second re-distribution pads extend in parallel in a first horizontal direction, and
the first re-distribution pads and the second re-distribution pads are alternately disposed in a second horizontal direction, the first horizontal direction and the second horizontal direction being perpendicular to each other.

### Claim 11 (depends on 10)

The semiconductor device of claim 10, wherein the second re-distribution pads are positioned at a higher level than the first re-distribution pads.

### Claim 12 (depends on 10)

The semiconductor device of claim 10, wherein the chip body includes:
first metal pads disposed in a first region; and
second metal pads disposed in a second region, and
wherein each of the first re-distribution pads includes:
a first via portion penetrating the lower dielectric layer to be coupled with the first metal pads; and
a first extended portion extending from the first via portion in the first horizontal direction, and
wherein each of the second re-distribution pads includes:
a second via portion penetrating the upper dielectric layer and the lower dielectric layer to be coupled with the second metal pads; and
a second extended portion extending from the second via portion in the first horizontal direction.

### Claim 13 (depends on 12)

The semiconductor device of claim 12, wherein:
the first re-distribution pads further include first pad portions corresponding to end portions of the first extended portions, respectively,
the second re-distribution pads further include second pad portions corresponding to end portions of the second extended portions, respectively, and
the first pad portions and the second pad portions are disposed near an edge of the chip body.

### Claim 14

A method of manufacturing a semiconductor device, comprising:
preparing a chip body with a first metal pad and a second metal pad;
forming a passivation layer on the chip body;
forming a lower dielectric layer on the passivation layer;
forming a first re-distribution pad on the lower dielectric layer;
forming an upper dielectric layer on the lower dielectric layer, the upper dielectric layer having a groove that exposes an upper surface of the first re-distribution pad; and
forming a second re-distribution pad on the upper dielectric layer.

### Claim 15 (depends on 14)

The method of claim 14, wherein forming the first re-distribution pad includes:
forming a lower hole that vertically penetrates the lower dielectric layer to expose an upper surface of the first metal pad;
forming a lower metal liner on the upper surface of the first metal pad, an inner wall of the lower hole, and an upper surface of the lower dielectric layer;
forming a first mask pattern with a first trench on the lower metal liner; and
forming the first re-distribution pad on the lower metal liner that is exposed in the first trench.

### Claim 16 (depends on 15)

The method of claim 15, wherein forming the second re-distribution pad includes:
forming an upper hole that exposes an upper surface of the second metal pad by vertically penetrating the upper dielectric layer and the lower dielectric layer;
forming an upper metal liner on the upper surface of the second metal pad, an inner wall of the upper hole, and an upper surface of the upper dielectric layer;
forming a second mask pattern with a second trench on the upper metal liner; and
forming the second re-distribution pad on the upper metal liner that is exposed in the second trench.

### Claim 17 (depends on 14)

The method of claim 14, wherein the first re-distribution pad includes:
a first via portion penetrating the lower dielectric layer and the passivation layer to be coupled with the first metal pad;
a first extended portion extending from the first via portion in a horizontal direction; and
a first pad portion corresponding to an end portion of the first extended portion, and
wherein:
the first via portion is disposed near a center of the chip body, and
the first pad portion is disposed near an edge of the chip body.

### Claim 18 (depends on 17)

The method of claim 17, wherein the second re-distribution pad includes:
a second via portion penetrating the upper dielectric layer, the lower dielectric layer, and the passivation layer to be coupled with the second metal pad;
a second extended portion extending from the second via portion in the horizontal direction; and
a second pad portion corresponding to an end portion of the second extended portion, and
wherein:
the second via portion is disposed near the center of the chip body, and
the second pad portion is disposed near the edge of the chip body.

### Claim 19 (depends on 14)

The method of claim 14, further comprising:
forming a protective dielectric layer that covers the first re-distribution pad and the second re-distribution pad on the upper dielectric layer,
wherein the protective dielectric layer includes a first connection hole that exposes a portion of the first re-distribution pad and includes a second connection hole that covers the second re-distribution pad.

### Claim 20 (depends on 19)

The method of claim 19, further comprising:
forming a first metal pillar in the first connection hole; and
forming a second metal pillar in the second connection hole.