# US 2023/0057504 A1 · Smooth transition for data streams with adjusted gain > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2023/0057504 A1 - Document ID: US20230057504A1 - Status: Published application - Kind: A1 - Application number: 17/818,994 - Filed: 2022-08-11 - Published: 2023-02-23 - Earliest claimed: 2020-02-18 - Assignees: Zeku, Inc. - Applicants: Zeku, Inc. - Inventors: Jifeng GENG; Hong Kui YANG - Web page: https://patentgrep.com/patent/US20230057504A1 ## CPC - H04L 25/03834: {using pulse shaping} - H04L 27/26265: {Arrangements for sidelobes suppression specially adapted to multicarrier systems, e.g. spectral precoding} - H04B 1/0475: {with means for limiting noise, interference or distortion (H04B1/0483 takes precedence)} - H04L 27/12: Modulator circuits; Transmitter circuits - H04L 27/2626: {Arrangements specific to the transmitter only} - H04B 2001/0425: {with linearisation using predistortion} - H04L: TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION (arrangements common to telegraphic and telephonic communication H04M) - H04B: TRANSMISSION ## Abstract Embodiments of apparatus and method for transition smoothing implementation on a stream of data are disclosed. In an example, a system on chip (SoC) for wireless communication includes a digital front-end. The digital front-end is configured to obtain a stream of data having one carrier or multi-carriers. The stream of data is divided into a plurality of blocks. The digital front-end is also configured to adjust a gain of the stream of data based on a predetermined frequency corresponding to a length of each of the plurality of blocks. The digital front-end is also configured to append a ramp-down tail sequence to a first block of the stream of data after a last sample of the first block, and generate a ramp-up head sequence for a second block immediately after the first block, based on a head sequence of the second block. ## Claims ### Claim 1 A system on chip (SoC) for wireless communication, comprising a digital front-end configured to: obtain a stream of data having at least one carrier, wherein the stream of data is divided into a plurality of blocks; adjust a gain of the stream of data at a predetermined frequency corresponding to a length of each of the plurality of blocks ; append a ramp-down tail sequence to a first block of the stream of data after a last sample of the first block; and generate a ramp-up head sequence for a second block immediately after the first block based on a head sequence of the second block. ### Claim 2 (depends on 1) The SoC of claim 1, wherein to append the ramp-down tail sequence, the digital front-end is further configured to: apply a ramp-down window to the last sample of the first block to generate the ramp-down tail sequence; and append the ramp-down tail sequence after the last sample of the first block. ### Claim 3 (depends on 1) The SoC of claim 1, wherein to generate the ramp-up head sequence, the digital front-end is further configured to apply a ramp-up window to the head sequence of the second block. ### Claim 4 (depends on 1) The SoC of claim 1, wherein to obtain the stream of data, the digital front-end is further configured to combine a plurality of asynchronized symbol streams having different component carriers in a time domain, wherein the at least one carrier of the stream of data includes the different component carriers of the plurality of asynchronized symbol streams. ### Claim 5 (depends on 4) The SoC of claim 4, wherein each of the plurality of asynchronized symbols streams comprises orthogonal frequency-division multiplexing (OFDM) symbols. ### Claim 6 (depends on 1) The SoC of claim 1, wherein the digital front-end is further configured to compensate a nonlinearity of the stream of data at the predetermined frequency. ### Claim 7 (depends on 6) The SoC of claim 6, wherein to compensate the nonlinearity, the digital front-end is further configured to apply a digital pre-distortion to the stream of data. ### Claim 8 (depends on 1) The SoC of claim 1, wherein the digital front-end is further configured to identify a block boundary of each of the plurality of blocks based on the predetermined frequency for adjusting the gain of the stream of data. ### Claim 9 (depends on 1) The SoC of claim 1, wherein a length of the ramp-down tail sequence of the first block equals a length of the ramp-up head sequence of the second block. ### Claim 10 (depends on 1) The SoC of claim 1, wherein the ramp-down tail sequence of the first block overlaps the ramp-up head sequence of the second block. ### Claim 11 A radio frequency (RF) chip comprising a digital front-end, wherein the digital front-end comprises: a multiplexer module configured to combine a plurality of orthogonal frequency-division multiplexing (OFDM) symbol streams having different component carriers in a time domain or to transform a single OFDM symbol stream to generate a stream of data having at least one carrier; a nonlinearity compensation module configured to: adjust a gain of the stream of data at a predetermined frequency corresponding to a length of each of a plurality of blocks; and apply a digital pre-distortion to the stream of data to compensate a nonlinearity of the stream of data, wherein the stream of data is divided into the plurality of blocks; and a transition smoothing module configured to apply soft edge pulse-shaping to smooth transitions of the plurality of blocks. ### Claim 12 (depends on 11) The RF chip of claim 11, wherein to apply soft edge pulse-shaping, the transition smoothing module is further configured to: append a ramp-down tail sequence to a first block of the stream of data after a last sample of the first block; and generate a ramp-up head sequence for a second block immediately after the first block, based on a head sequence of the second block. ### Claim 13 (depends on 12) The RF chip of claim 12, wherein to append the ramp-down tail sequence, the transition smoothing module is further configured to: apply a ramp-down window to the last sample of the first block to generate the ramp-down tail sequence; and append the ramp-down tail sequence after the last sample of the first block. ### Claim 14 (depends on 12) The RF chip of claim 12, wherein to generate the ramp-up head sequence, the transition smoothing module is further configured to apply a ramp-up window to the head sequence of the second block. ### Claim 15 (depends on 12) The RF chip of claim 12, wherein a length of the ramp-down tail sequence of the first block equals a length of the ramp-up head sequence of the second block. ### Claim 16 (depends on 12) The RF chip of claim 12, wherein the ramp-down tail sequence of the first block overlaps the ramp-up head sequence of the second block. ### Claim 17 A method implemented by a system on chip (SoC) for wireless communication, comprising: obtaining a stream of data having at least one carrier, wherein the stream of data is divided into a plurality of blocks; adjusting a gain of the stream of data based on a predetermined frequency corresponding to a length of each of the plurality of blocks; appending a ramp-down tail sequence to a first block of the stream of data after a last sample of the first block; and generating a ramp-up head sequence for a second block immediately after the first block, based on a head sequence of the second block. ### Claim 18 (depends on 17) The method of claim 17, the method further comprising combining a plurality of asynchronized symbol streams having different component carriers in a time domain to generate the stream of data. ### Claim 19 (depends on 17) The method of claim 17, wherein a length of the ramp-down tail sequence of the first block equals a length of the ramp-up head sequence of the second block. ### Claim 20 (depends on 17) The method of claim 17, wherein the ramp-down tail sequence of the first block overlaps the ramp-up head sequence of the second block.