# US 2023/0057480 A1 · Semiconductor structure and method for forming same

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- Number: US 2023/0057480 A1
- Document ID: US20230057480A1
- Status: Published application
- Kind: A1
- Application number: 17/810,634
- Filed: 2022-07-04
- Published: 2023-02-23
- Earliest claimed: 2021-08-17
- Assignees: Changxin Memory Technologies, Inc.; Beijing Superstring Academy of Memory Technology
- Applicants: Changxin Memory Technologies, Inc.; Beijing Superstring Academy of Memory Technology
- Inventors: Guangsu SHAO; Deyuan XIAO; Yunsong QIU; Minmin WU
- Web page: https://patentgrep.com/patent/US20230057480A1

## CPC

- H10B 12/482: {Bit lines}
- H10B 12/053: {the transistor being at least partially in a trench in the substrate (vertical transistor in combination with a capacitor formed in a substrate trench H10B12/0383)}
- H10B 12/30: {DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells}
- H10B 12/488: {Word lines}
- H10D 84/01: Manufacture or treatment
- H10D 84/0158: {the components including FinFETs}
- H10D 84/80: characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs (H10D84/40 takes precedence)
- H10P 50/283: {by chemical means}
- H10W 10/014: {using trench refilling with dielectric materials, e.g. shallow trench isolations}
- H10W 10/17: formed using trench refilling with dielectric materials, e.g. shallow trench isolations
- G11C 7/18: Bit line organisation; Bit line lay-out
- H10B 12/485: {Bit line contacts}
- H10B: ELECTRONIC MEMORY DEVICES
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

A method for forming a semiconductor structure includes: providing a semiconductor substrate including a plurality of first semiconductor pillars and bit line isolation trenches arranged at intervals in a first direction; in which the bit line isolation trenches extend in a second direction, the first direction being perpendicular to the second direction; forming a bit line isolation layer in a bit line isolation trench; in which a gap is provided between the bit line isolation layer and the bit line isolation trench, in which the gap is located at a bottom corner of the bit line isolation trench and extends in the second direction, and exposes part of the bottom of the bit line isolation trench; etching a first semiconductor pillar in the first direction through the gap to form a bit line trench; forming a bit line in the bit line trench.

## Claims

### Claim 1

A method for forming a semiconductor device, comprising:
providing a semiconductor substrate comprising a plurality of first semiconductor pillars and bit line isolation trenches arranged at intervals in a first direction; wherein the bit line isolation trenches extend in a second direction, and the first direction is perpendicular to the second direction;
forming a bit line isolation layer in a bit line isolation trench; wherein a gap is provided between the bit line isolation layer and the bit line isolation trench, wherein the gap is located at a bottom corner of the bit line isolation trench and extends in the second direction, and the gap exposes part of a bottom of the bit line isolation trench;
etching a first semiconductor pillar in the first direction through the gap to form a bit line trench; and
forming a bit line in the bit line trench.

### Claim 2 (depends on 1)

The method of claim 1, wherein forming the bit line isolation layer in the bit line isolation trench comprises:
forming an initial bit line isolation layer in the bit line isolation trench; and
removing part of the initial bit line isolation layer to form the bit line isolation layer and the gap.

### Claim 3 (depends on 2)

The method of claim 2, wherein forming the initial bit line isolation layer in the bit line isolation trench comprises:
forming a first initial isolation layer and a second initial isolation layer in sequence in the bit line isolation trench;
removing part of the second initial isolation layer and part of the first initial isolation layer in sequence by etching in a third direction to form a first etching groove; wherein the first etching groove exposes a first sidewall of the bit line isolation trench and another part of the bottom of the bit line isolation trench; and the third direction is a depth direction of the bit line isolation trench; and
filling an isolation material in the first etching groove to form a third initial isolation layer,
wherein remaining first initial isolation layer, remaining second initial isolation layer and the third initial isolation layer constitute the initial bit line isolation layer.

### Claim 4 (depends on 3)

The method of claim 3, wherein removing the part of the initial bit line isolation layer to form the bit line isolation layer and the gap comprises:
etching the remaining second initial isolation layer and the remaining first initial isolation layer in sequence in the third direction at an end of the bit line isolation trench to form at least one opening; and
removing a further remaining first initial isolation layer of the initial bit line isolation layer through the opening to form the bit line isolation layer and the gap.

### Claim 5 (depends on 4)

The method of claim 4, wherein etching the first semiconductor pillar in the first direction through the gap to form the bit line trench comprises:
partially etching the first semiconductor pillar in the first direction through the gap to form a second etching groove; wherein a dimension of the second etching groove in the third direction is equal to a dimension of the gap in the third direction, and a dimension of the second etching groove in the first direction is smaller than a dimension of the first semiconductor pillar in the first direction;
the second etching groove and the gap jointly constitute the bit line trench.

### Claim 6 (depends on 4)

The method of claim 4, wherein etching the first semiconductor pillar in the first direction through the gap to form the bit line trench comprises:
fully etching the first semiconductor pillar in the first direction through the gap to form a third etching groove; wherein a dimension of the third etching groove in the third direction is equal to a dimension of the gap in the third direction, and a dimension of the third etching groove in the first direction is equal to a dimension of the first semiconductor pillar in the first direction;
the third etching groove and the gap jointly constitute the bit line trench.

### Claim 7 (depends on 5)

The method of claim 5, further comprising: before forming the bit line,
etching a further remaining second initial isolation layer in the third direction to form a fourth etching groove; wherein the fourth etching groove expose the gap and a second sidewall of the bit line isolation trench; and
forming the bit line in the bit line trench through the fourth etching groove.

### Claim 8 (depends on 7)

The method of claim 7, wherein forming the bit line in the bit line trench through the fourth etching groove comprises:
forming an initial bit line layer in the fourth etching groove and the bit line trench; and
etching back the initial bit line layer to remove the initial bit line layer located in the fourth etching groove to form the bit line.

### Claim 9 (depends on 8)

The method of claim 8, further comprising: after forming the bit line,
filling an insulating material in the fourth etching groove to form an insulating layer;
wherein a top surface of the insulating layer is flush with a top surface of the third initial isolation layer.

### Claim 10 (depends on 9)

The method of claim 9, further comprising: after forming the insulating layer,
forming a plurality of word line trenches in the first semiconductor pillars, wherein the word line trenches extend in the first direction; and
forming word lines in the word line trenches.

### Claim 11 (depends on 10)

The method of claim 10, wherein forming the plurality of word line trenches in the first semiconductor pillars comprises:
etching the first semiconductor pillars in the third direction to form a plurality of word line trenches and second semiconductor pillars arranged at intervals in the second direction;
wherein a bottom of a word line trench is above a top of the bit line.

### Claim 12 (depends on 11)

The method of claim 11, wherein forming the word lines in the word line trenches comprises:
forming gate insulating layers on sidewalls of a word line trench;
forming a bottom initial barrier layer, an initial word line layer and a top initial barrier layer in sequence in the word line trench with the gate insulating layers formed; and
etching part of the top initial barrier layer, part of the initial word line layer and part of the bottom initial barrier layer in sequence in the third direction to form a word line isolation trench located at a center of the word line trench, remaining initial word line layer constituting a word line;
wherein a part of the bottom initial barrier layer is remained at a bottom of the word line isolation trench.

### Claim 13 (depends on 12)

The method of claim 12, further comprising: after forming the word lines,
filling an insulating material in the word line isolation trench to form a word line isolation layer.

### Claim 14

A semiconductor structure, at least comprising:
a semiconductor substrate comprising a plurality of first semiconductor pillars and bit line isolation trenches arranged at intervals in a first direction; wherein the bit line isolation trenches extend in a second direction, and the first direction is perpendicular to the second direction;
bit line isolation layers, wherein a bit line isolation layer is located in a bit line isolation trench; and
bit lines, wherein part of a bit line is buried at a bottom of a semiconductor pillar, and another part of the bit line is buried at a bottom corner between the bit line isolation layer and the bit line isolation trench.

### Claim 15 (depends on 14)

The semiconductor structure of claim 14, wherein the semiconductor substrate further comprises a plurality of word line trenches and second semiconductor pillars arranged at intervals in the second direction; and the semiconductor structure further comprises:
gate insulating layers located on sidewalls of the word line trenches;
word line isolation layers, wherein a word line isolation layer is located at a center of a word line trench, wherein a top surface of the word line isolation layer is flush with a top surface of a second semiconductor pillar; a dimension of the word line isolation layer in a third direction is smaller than a dimension of the word line trench in the third direction; wherein the third direction is a depth direction of the word line trench;
top barrier layers, wherein a top barrier layer is located between the gate insulating layers at a top of the word line trench and a corresponding word line isolation layer;
word lines, wherein a word line is located between the gate insulating layers in a middle of the word line trench and the corresponding word line isolation layer; and
bottom barrier layers, wherein a bottom barrier layer is located at a bottom of the word line trench with the gate insulating layers formed, and is in contact with the word line and part of the word line isolation layer.

### Claim 16 (depends on 15)

The semiconductor structure of claim 15, further comprising channels;
wherein a channel is located between two adjacent gate insulating layers, and the channel is a second semiconductor pillar region corresponding to the word line and between the two adjacent gate insulating layers.