# US 2023/0057083 A1 · Hot page detection by sampling tlb residency

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- Number: US 2023/0057083 A1
- Document ID: US20230057083A1
- Status: Published application
- Kind: A1
- Application number: 17/818,828
- Filed: 2022-08-10
- Published: 2023-02-23
- Earliest claimed: 2022-08-10
- Assignees: Intel Corporation
- Applicants: Intel Corporation
- Inventors: Andy Rudoff
- Web page: https://patentgrep.com/patent/US20230057083A1

## CPC

- G06F 12/1027: using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
- G06F 12/122: of the least frequently used [LFU] type, e.g. with individual count value
- G06F 12/08: in hierarchically structured memory systems, e.g. virtual memory systems
- G06F 12/0811: with multilevel cache hierarchies
- G06F 2212/1016: Performance improvement
- G06F 2212/1024: Latency reduction
- G06F 2212/681: Multi-level TLB, e.g. microTLB and main TLB
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

The disclosed technology provides for an improved memory tiering arrangement. In one aspect, an apparatus includes a sampling register and logic, responsive to sequential read requests, to read page data entries stored in successive locations in a TLB and provide page data from the page data entries as sequential outputs of the sampling register. In another aspect, a method includes generating a page residency list based on scanning, via a sampling register, page data entries stored in successive locations in a TLB, determining, for each page, whether the respective page is a hot page or a cold page based on the page residency list, and assigning hot pages to a first memory tier and cold pages to a second memory tier. Scanning page data entries stored in the TLB can include issuing a sequence of read requests to the sampling register sufficient to read all entries in the TLB.

## Claims

### Claim 1

A semiconductor apparatus comprising:
one or more substrates;
a sampling register coupled to the one or more substrates; and
logic coupled to the one or more substrates, wherein the logic is implemented at least partly in one or more of configurable or fixed-functionality hardware, the logic to:
responsive to sequential read requests to the sampling register, read page data entries stored in successive locations in a translation lookaside buffer (TLB); and
provide page data from the page data entries as sequential outputs of the sampling register.

### Claim 2 (depends on 1)

The semiconductor apparatus of claim 1, wherein the sampling register includes a page identifier (ID) field, and the sequential outputs each include one or more page identifiers for the page data at the respective location in the TLB.

### Claim 3 (depends on 2)

The semiconductor apparatus of claim 2, wherein the sampling register further includes one or more of a valid bit field or a page size field.

### Claim 4 (depends on 1)

The semiconductor apparatus of claim 1, wherein the logic is to scan the TLB by reading successive locations in the TLB and, after reading an end location of the TLB, return to a beginning location of the TLB.

### Claim 5 (depends on 4)

The semiconductor apparatus of claim 4, wherein the logic is to scan the TLB on one of a column-by column basis or a row-by row basis.

### Claim 6 (depends on 1)

The semiconductor apparatus of claim 1, wherein each read request results in reading a single page table entry in the TLB.

### Claim 7 (depends on 1)

The semiconductor apparatus of claim 1, wherein for each read request the logic is to read a number of page table entries based on a type of the respective read request.

### Claim 8

A computing system comprising:
a first memory tier;
a second memory tier; and
a processor coupled to the first memory tier and to the second memory tier, wherein the processor includes a sampling register and logic implemented at least partly in one or more of configurable or fixed-functionality hardware, the logic to:
responsive to sequential read requests to the sampling register, read page data entries stored in successive locations in a translation lookaside buffer (TLB); and
provide page data from the page data entries as sequential outputs of the sampling register.

### Claim 9 (depends on 8)

The computing system of claim 8, wherein the sampling register includes a page identifier (ID) field, and the sequential outputs each include one or more page identifiers for the page data at the respective location in the TLB.

### Claim 10 (depends on 9)

The computing system of claim 9, wherein the logic is to scan the TLB by reading successive locations in the TLB and, after reading an end location of the TLB, return to a beginning location of the TLB.

### Claim 11 (depends on 10)

The computing system of claim 10, wherein the logic is to scan the TLB on one of a column-by column basis or a row-by row basis, and wherein each read request results in reading a single page table entry in the TLB.

### Claim 12 (depends on 10)

The computing system of claim 10, further comprising a memory to store instructions which, when executed by the processor, cause the computing system to:
generate a page residency list based on scanning the TLB via the sampling register;
determine, for each page of a plurality of pages, whether the respective page is a hot page or a cold page based on the page residency list; and
assign hot pages to the first memory tier and cold pages to the second memory tier.

### Claim 13 (depends on 12)

The computing system of claim 12, wherein the read requests are issued at a frequency based on a sampling frequency parameter, and wherein the sampling frequency parameter is set based on a size of the TLB.

### Claim 14 (depends on 12)

The computing system of claim 12, wherein determining whether the respective page is a hot page or a cold page is further based on a threshold residency parameter, and wherein the threshold residency parameter is set based on a residency decay rate.

### Claim 15

A method comprising:
generating a page residency list based on scanning, via a sampling register, page data entries stored in successive locations in a translation lookaside buffer (TLB);
determining, for each page of a plurality of pages, whether the respective page is a hot page or a cold page based on the page residency list; and
assigning hot pages to a first memory tier and cold pages to a second memory tier.

### Claim 16 (depends on 15)

The method of claim 15, wherein scanning, via the sampling register, page data entries stored in the TLB comprises issuing a sequence of read requests to the sampling register sufficient to read all entries in the TLB.

### Claim 17 (depends on 16)

The method of claim 16, wherein the read requests are issued at a frequency based on a sampling frequency parameter.

### Claim 18 (depends on 17)

The method of claim 17, wherein the sampling frequency parameter is set based on a size of the TLB.

### Claim 19 (depends on 15)

The method of claim 15, wherein determining whether the respective page is a hot page or a cold page is further based on a threshold residency parameter.

### Claim 20 (depends on 19)

The method of claim 19, wherein the threshold residency parameter is set based on a residency decay rate.