# US 2023/0057034 A1 · Method for viewing simulation signals of digital products and simulation system > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2023/0057034 A1 - Document ID: US20230057034A1 - Status: Published application - Kind: A1 - Application number: 17/792,480 - Filed: 2020-03-25 - Published: 2023-02-23 - Earliest claimed: 2019-12-06 - Assignees: Shenzhen Guoweixin Technology Go., Ltd - Applicants: Shenzhen Guoweixin Technology Go., Ltd - Inventors: Kaipeng LIN; Yanrong LI; Xiaoli HUANG - Web page: https://patentgrep.com/patent/US20230057034A1 ## CPC - G06F 30/343: Logical level - G06F 30/3308: using simulation - G06F 30/3323: using formal methods, e.g. equivalence checking or property checking - G06F 9/455: Emulation; Interpretation; Software simulation, e.g. virtualisation or emulation of application or operating system execution engines - G06F 11/07: Responding to the occurrence of a fault, e.g. fault tolerance - G06F 30/331: with hardware acceleration, e.g. by using field programmable gate array [FPGA] or emulation - G06F 30/34: for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD] - G06F 30/367: Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods - G06F 30/398: Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] (optical proximity correction [OPC] design processes G03F1/36) - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract The present invention discloses a method for viewing simulation signals of digital products and a simulation system, the method includes: when performing FPGA simulation on digital products, reading out all external port status data of digital products in real time and recording, meanwhile reading out all internal status data of digital products once every interval time and recording; after completing the simulation, when needing a back trace to check the data of digital products in a certain clock cycle, reading out the internal status data of digital products stored at the last time point before this clock cycle and the external port status data at said time point in the recorded simulation data; and taking the read-out data as an initial status data of the FPGA, then reading out all internal status data of digital products clock by clock until running to the clock cycle that needs to be viewed. ## Claims ### Claim 1 A method for viewing simulation signals of digital products, comprising: when performing FPGA simulation on digital products, reading out all external port status data of digital products in real time and recording, meanwhile reading out all internal status data of digital products once every interval time and recording; after completing the simulation, when needing a back trace to check the data of digital products in a certain clock cycle, reading out the internal status data of digital products stored at the last time point before this clock cycle and the external port status data at said time point in the recorded simulation data; and loading said digital products into a FPGA, setting the external port status data and the internal status data recorded at said time point as an initial status data of digital products, starting said FPGA to run and read out all internal status data of digital products clock by clock until running to the clock cycle that needs to be viewed. ### Claim 2 (depends on 1) The method for viewing simulation signals of digital products according claim 1, wherein when the external port status data and the internal status data of digital products are recorded, the serial number of the clock cycle is taken as a timestamp to store the external port status data and the internal status data of digital products as ordered structured data. ### Claim 3 (depends on 1) The method for viewing simulation signals of digital products according claim 1, wherein a static probe detection method is adopted to read out all external port status data of digital products. ### Claim 4 (depends on 1) The method for viewing simulation signals of digital products according claim 1, wherein a dynamic probe detection method is adopted to read out all internal status data of digital products. ### Claim 5 (depends on 1) The method for viewing simulation signals of digital products according claim 1, wherein when reading out all internal status data of digital products once every interval time, the interval time is the same every times. ### Claim 6 (depends on 5) The method for viewing simulation signals of digital products according claim 5, wherein each interval time is 1 million clock cycles. ### Claim 7 (depends on 1) The method for viewing simulation signals of digital products according claim 1, wherein when reading out all internal status data of digital products once every interval time, the interval time may be different every times. ### Claim 8 (depends on 1) A simulation system of a digital product, which uses the method for viewing simulation signals of digital products mentioned in claim 1, comprising an FPGA, a controller, and a storage device, wherein, said FPGA is used to load digital products and perform simulation verification; said controller is used to read out all external port status data of digital products in real time, and read out all internal status data of digital products once every interval time, when performing FPGA simulation on said digital products; said storage device is used to store the simulation data read out by said controller; after completing the simulation, when needing a back trace to check the data of digital products in a certain clock cycle, said controller reads out the internal status data of digital products recorded at the last time point before this clock cycle and the external port status data at said time point in the simulation data recorded in said storage device, then said controller loads said digital products into said FPGA, sets the external port status data and the internal status data recorded at said time point as an initial status data of digital products, starts said FPGA to run and read out all internal status data of digital products clock by clock until it runs to the clock cycle that needs to be viewed. ### Claim 9 (depends on 8) The simulation system of digital products according to claim 8, wherein after said controller has read out the external port status data and the internal status data of digital products, it takes the serial number of the clock cycle as a timestamp to store the external port data and the internal status data of digital products as ordered structured data and stores them in said storage device. ### Claim 10 (depends on 8) The simulation system of digital products according to claim 8, wherein said controller adopts a static probe detection method to read out all external port status data of digital products, and adopts a dynamic probe detection method to read out all internal status data of digital products.