# US 2023/0056957 A1 · Internal device sequencer for testing mode

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- Number: US 2023/0056957 A1
- Document ID: US20230056957A1
- Status: Published application
- Kind: A1
- Application number: 17/409,633
- Filed: 2021-08-23
- Published: 2023-02-23
- Earliest claimed: 2021-08-23
- Assignees: Texas Instruments Incorporated
- Applicants: Texas Instruments Incorporated
- Inventors: Sandeep KALYADAN; Krishnamurthy Ganapathi SHANKAR; Venkatesh GUDURI
- Web page: https://patentgrep.com/patent/US20230056957A1

## CPC

- G01R 31/2827: {Testing of electronic protection circuits (testing switches G01R31/327; checking alarm systems G08B29/00; self test of summation current transformers H02H3/335)}
- G01R 31/2621: {for testing field effect transistors, i.e. FET's}
- G01R: MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES (indicating correct tuning of resonant circuits H03J3/12)

## Abstract

A device includes FETs with control terminals. A gate driver circuit causes the FETs to turn on and to enter a high-impedance state in response to an OCP signal. A current sense circuit senses an FET current through the FETs and sends the OCP signal to the gate driver circuit when the FET current exceeds an OCP current for longer than an OCP deglitch period. A test sequencer, in response to receiving an external test mode signal, sets the OCP current to a preset OCP test current, sets the OCP deglitch period to a preset OCP deglitch test period, and causes the gate driver circuit to turn on the plurality of FETs.

## Claims

### Claim 1

A device, comprising:
a plurality of field-effect transistors (FETs), each of the FETs having a control terminal;
a gate driver circuit coupled to the control terminal of each of the plurality of FETs and configured to:
cause the plurality of FETs to turn on; and
cause the plurality of FETs to enter a high-impedance state in response to receiving an over-current protection (OCP) signal;
a current sense circuit coupled to the plurality of FETs and configured to sense an FET current passing through the plurality of FETs and to send the OCP signal to the gate driver circuit when the FET current exceeds an OCP current for a period of time longer than an OCP deglitch period; and
a test sequencer coupled to the gate driver circuit and the current sense circuit, the test sequencer configured to, in response to receiving an external test mode signal:
set the OCP current to a preset OCP test current;
set the OCP deglitch period to a preset OCP deglitch test period; and
cause the gate driver circuit to turn on the plurality of FETs.

### Claim 2 (depends on 1)

The device of claim 1, wherein the current sense circuit is coupled to an output pin of the device and configured to produce an IPROPI signal on the output pin, the IPROPI signal proportional to the FET current.

### Claim 3 (depends on 2)

The device of claim 2, wherein the IPROPI signal is a current proportional to the FET current.

### Claim 4 (depends on 1)

The device of claim 1, wherein the current sense circuit is configured to sense an FET current passing through the plurality of FETs using a current-sharing MOSFET coupled to the source, gate, and drain of a first FET of the plurality of FETS.

### Claim 5 (depends on 1)

The device of claim 1, wherein the external test mode signal comprises a voltage applied to a digital input pin of the device, the voltage exceeding a preset test mode threshold value.

### Claim 6 (depends on 5)

The device of claim 5, wherein the preset test mode threshold value is five volts and the external test mode signal comprises a seven volt signal.

### Claim 7 (depends on 1)

The device of claim 1, wherein the preset OCP test current is less than an OCP current used in non-test mode operation of the device.

### Claim 8 (depends on 7)

The device of claim 7, wherein the preset OCP test current is one of 200 milliamps and 4 amps.

### Claim 9 (depends on 1)

The device of claim 1, wherein the preset OCP deglitch test period is a value greater than an OCP deglitch period used in non-test mode operation of the device.

### Claim 10 (depends on 9)

The device of claim 9, wherein the preset OCP deglitch test period is 1 millisecond.

### Claim 11

A method of operating a field effect transistor (FET) device having at least one FET, comprising:
receiving an external test mode signal and, in response thereto:
setting an over-current protection (OCP) current of a current sense circuit of the FET device to a preset OCP test current;
setting an OCP deglitch period of the current sense circuit to a preset OCP deglitch test period; and
causing a gate driver circuit of the FET device to turn on one or more FETs of the FET device.

### Claim 12 (depends on 11)

The method of claim 11, further comprising:
sensing an FET current through the one or more FETs using a current-sharing MOSFET; and
causing the one or more FETs to enter a high-impedance state in response to the FET current exceeding the OCP current for a period of time longer than the OCP deglitch period.

### Claim 13 (depends on 12)

The method of claim 12, further comprising generating an IPROPI signal on an output pin of the FET device, the IPROPI signal proportional to the FET current.

### Claim 14 (depends on 13)

The method of claim 13, wherein the IPROPI signal is a current proportional to the FET current.

### Claim 15 (depends on 11)

The method of claim 11, wherein receiving the external test mode signal comprises sensing a voltage applied to a digital input pin of the FET device, where the voltage exceeds a preset test mode threshold value.

### Claim 16 (depends on 15)

The method of claim 15, wherein the preset test mode threshold value is five volts and the external test mode signal comprises a seven volt signal.

### Claim 17 (depends on 11)

The method of claim 11, wherein the preset OCP test current is less than an OCP current used in non-test mode operation of the FET device.

### Claim 18 (depends on 17)

The method of claim 17, wherein the preset OCP test current is one of 200 milliamps and 4 amps.

### Claim 19 (depends on 11)

The method of claim 11, wherein the preset OCP deglitch test period is a value greater than an OCP deglitch period used in non-test mode operation of the FET device.

### Claim 20 (depends on 19)

The method of claim 19, wherein the preset OCP deglitch test period is 1 millisecond.