# US 2023/0056897 A1 · Display device and method of manufacturing the same

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- Number: US 2023/0056897 A1
- Document ID: US20230056897A1
- Status: Published application
- Kind: A1
- Application number: 17/841,904
- Filed: 2022-06-16
- Published: 2023-02-23
- Earliest claimed: 2021-08-17
- Assignees: Samsung Display Co., Ltd.
- Applicants: Samsung Display Co., Ltd.
- Inventors: MYEONGHO KIM; JAYBUM KIM; KYOUNG SEOK SON; SEUNGJUN LEE; SEUNGHUN LEE; JUN HYUNG LIM
- Web page: https://patentgrep.com/patent/US20230056897A1

## CPC

- G09G 3/3241: the current through the light-emitting element being set using a data current provided by the data driver, e.g. by using a two-transistor current mirror
- H10D 86/481: {integrated with passive devices, e.g. auxiliary capacitors}
- H10D 86/021: {of multiple TFTs}
- H10D 86/423: {comprising semiconductor materials not belonging to the Group IV, e.g. InGaZnO}
- H10D 86/441: {Interconnections, e.g. scanning lines}
- H10D 86/60: wherein the TFTs are in active matrices
- H10K 59/1216: {the pixel elements being capacitors}
- G09G 3/32: semiconductive, e.g. using light-emitting diodes [LED]
- G09G 2300/0426: Layout of electrodes and connections
- G09G 2300/0819: used for counteracting undesired variations, e.g. feedback or autozeroing
- G09G 2300/0852: being a dynamic memory with more than one capacitor
- G09G 2300/0876: Supplementary capacities in pixels having special driving circuits and electrodes instead of being connected to common electrode or ground; Use of additional capacitively coupled compensation electrodes
- G09G 2310/0251: Precharge or discharge of pixel before applying new pixel voltage
- G09G: ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION (arrangements for transferring data between digital computers and displays G06F3/14; static indicating arrangements comprising an association of a number of separate sources or light control cells G09F9/00; static indicating arrangements comprising integral associations of a number of light sources H01J, H01K, H10H, H05B33/12; scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission, details thereof H04N1/00)
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10K: ORGANIC ELECTRIC SOLID-STATE DEVICES

## Abstract

A display device includes a first semiconductor layer, a first conductive layer disposed on the first semiconductor layer and including a first capacitor electrode at least partially overlapping the first semiconductor layer in a plan view to constitute a first transistor, a second capacitor electrode disposed on the first conductive layer and overlapping the first capacitor electrode in a plan view to constitute a first capacitor, a second semiconductor layer disposed on the second capacitor electrode and including a third capacitor electrode overlapping the second capacitor electrode in a plan view to constitute a second capacitor, a second conductive layer disposed on the second semiconductor layer and at least partially overlapping the second semiconductor layer, and a third conductive layer disposed over the second conductive layer to implement a high-resolution image by overlapping the first capacitor electrode, the second capacitor electrode, and the third capacitor electrode.

## Claims

### Claim 1

A display device comprising:
a first semiconductor layer;
a first conductive layer disposed on the first semiconductor layer and including a first capacitor electrode at least partially overlapping the first semiconductor layer in a plan view to constitute a first transistor;
a second capacitor electrode disposed on the first conductive layer and overlapping the first capacitor electrode in a plan view to constitute a first capacitor;
a second semiconductor layer disposed on the second capacitor electrode and including a third capacitor electrode overlapping the second capacitor electrode in a plan view to constitute a second capacitor;
a second conductive layer disposed on the second semiconductor layer and at least partially overlapping the second semiconductor layer; and
a third conductive layer disposed on the second conductive layer.

### Claim 2 (depends on 1)

The display device of claim 1, wherein the second capacitor electrode includes a first through hole exposing a portion of an upper surface of the first capacitor electrode, and the third capacitor electrode includes a second through hole overlapping the first through hole to expose the portion of the upper surface of the first capacitor electrode.

### Claim 3 (depends on 2)

The display device of claim 2, wherein the third conductive layer includes a first bridge electrode connecting the upper surface of the first capacitor electrode exposed through the first through hole and the second through hole, and the second semiconductor layer.

### Claim 4 (depends on 1)

The display device of claim 1, wherein the third capacitor electrode includes a third through hole exposing a portion of an upper surface of the second capacitor electrode.

### Claim 5 (depends on 4)

The display device of claim 4, wherein the third conductive layer includes a second bridge electrode connecting the portion of the upper surface of the second capacitor electrode exposed through the third through hole, and the second semiconductor layer.

### Claim 6 (depends on 1)

The display device of claim 1, wherein the second semiconductor layer and the second conductive layer constitute a second transistor, a third transistor, a fourth transistor, and a fifth transistor, and
wherein the first semiconductor layer and the first conductive layer constitute a sixth transistor, a seventh transistor, an eighth transistor, and a ninth transistor.

### Claim 7 (depends on 6)

The display device of claim 6, wherein the third conductive layer includes:
a first initialization voltage line connected to an input terminal of the fourth transistor; and
a second initialization voltage line connected to an input terminal of the seventh transistor while being spaced apart from the first initialization voltage line.

### Claim 8 (depends on 1)

The display device of claim 1, wherein an area of the second capacitor electrode is larger than an area of the first capacitor electrode and the second capacitor electrode completely covers the first capacitor electrode in a plan view.

### Claim 9 (depends on 8)

The display device of claim 8, wherein a size of a first overlapping area, which is an overlapping area between the first capacitor electrode and the second capacitor electrode in a plan view, is equal to a size of a second overlapping area, which is an overlapping area between the second capacitor electrode and the third capacitor electrode, in a plan view.

### Claim 10 (depends on 1)

The display device of claim 1, wherein the second semiconductor layer includes an oxide semiconductor.

### Claim 11 (depends on 10)

The display device of claim 10, wherein the second semiconductor layer includes a first oxide semiconductor pattern and a second oxide semiconductor pattern spaced apart from the first oxide semiconductor pattern.

### Claim 12 (depends on 11)

The display device of claim 11, wherein the third capacitor electrode is disposed between the first oxide semiconductor pattern and the second oxide semiconductor pattern in a plan view.

### Claim 13

A display device comprising:
a first semiconductor layer;
a first conductive layer disposed on the first semiconductor layer and including a first capacitor electrode at least partially overlapping the first semiconductor layer in a plan view to constitute a first transistor;
a second capacitor electrode disposed on the first conductive layer and including an overlapping area overlapping the first capacitor electrode in a plan view to constitute a first capacitor, the second capacitor electrode including a protruding area protruding from the overlapping area;
a second semiconductor layer disposed on the second capacitor electrode and including a third capacitor electrode overlapping the second capacitor electrode in a plan view to constitute a second capacitor, the third capacitor electrode exposing the protruding area in a plan view;
a second conductive layer disposed on the second semiconductor layer and at least partially overlapping the second semiconductor layer; and
a third conductive layer disposed on the second conductive layer.

### Claim 14 (depends on 13)

The display device of claim 13, wherein the second semiconductor layer includes an oxide semiconductor.

### Claim 15 (depends on 14)

The display device of claim 14, wherein the second semiconductor layer includes a first oxide semiconductor pattern spaced apart from the third capacitor electrode in a first direction.

### Claim 16 (depends on 15)

The display device of claim 15, wherein the third conductive layer includes a first bridge electrode connected to the first oxide semiconductor pattern and the protruding area of the second capacitor electrode.

### Claim 17 (depends on 15)

The display device of claim 15, wherein the protruding area of the second capacitor electrode protrudes from the overlapping area of the second capacitor electrode in a second direction perpendicular to the first direction.

### Claim 18

A method of manufacturing a display device, the method comprising:
forming a first semiconductor layer on a substrate;
forming a first insulating layer covering the first semiconductor layer;
forming, on the first insulating layer, a first conductive layer including a first capacitor electrode at least partially overlapping the first semiconductor layer to constitute a first transistor;
forming a second insulating layer covering the first conductive layer;
forming, on the second insulating layer, a second capacitor electrode overlapping the first capacitor electrode to constitute a first capacitor;
forming a third insulating layer covering the second capacitor electrode;
forming, on the third insulating layer, a second semiconductor layer including a third capacitor electrode overlapping the second capacitor electrode to constitute a second capacitor;
forming a fourth insulating layer covering the second semiconductor layer; and
forming a second conductive layer disposed on the fourth insulating layer and at least partially overlapping the second semiconductor layer.

### Claim 19 (depends on 18)

The method of claim 18, wherein the second semiconductor layer includes an oxide semiconductor.

### Claim 20 (depends on 19)

The method of claim 19, further comprising: implanting impurities into the second semiconductor layer by using the second conductive layer as a mask, after forming the second conductive layer.