# US 2023/0056891 A1 · Controlling bit line pre-charge voltage separately for multi-level memory cells and single-level memory cells to reduce peak current consumption > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2023/0056891 A1 - Document ID: US20230056891A1 - Status: Published application - Kind: A1 - Application number: 17/406,224 - Filed: 2021-08-19 - Published: 2023-02-23 - Earliest claimed: 2021-08-19 - Assignees: SanDisk Technologies LLC - Applicants: SanDisk Technologies LLC - Inventors: Yu-Chung Lien; Deepanshu Dutta; Jiahui Yuan - Web page: https://patentgrep.com/patent/US20230056891A1 ## CPC - G11C 16/0483: {comprising cells having several storage transistors connected in series} - G11C 16/102: {External programming circuits, e.g. EPROM programmers; In-circuit programming or reprogramming; EPROM emulators} - G11C 11/5628: {Programming or writing circuits; Data input circuits} - G11C 11/5642: {Sensing or reading circuits; Data output circuits} - G11C 16/0433: {comprising cells containing a single floating gate transistor and one or more separate select transistors} - G11C 16/08: Address circuits; Decoders; Word-line control circuits - G11C 16/10: Programming or data input circuits - G11C 16/24: Bit-line control circuits - G11C 16/26: Sensing or reading circuits; Data output circuits - G11C 16/30: Power supply circuits - G11C 16/32: Timing circuits - G11C 16/3459: {Circuits or methods to verify correct programming of nonvolatile memory cells} - G11C 2211/5621: Multilevel programming verification - G11C 2211/5641: Multilevel memory having cells with different number of storage levels - H10B 43/27: the channels comprising vertical portions, e.g. U-shaped channels - G11C: STATIC STORES (semiconductor memory devices H10B) - H10B: ELECTRONIC MEMORY DEVICES ## Abstract Apparatuses and techniques are described for controlling a bit line pre-charge voltage in a program operation based on a number of bits per cell, with a goal to reduce peak current consumption. In one aspect, the ramp up of a bit line voltage to an inhibit level is optimized according to the number of bits per cell. The ramp up can involve increasing the bit line voltage from an initial level to a target voltage at a regulated rate, then increasing the bit line voltage from the target voltage to a final voltage at an unregulated rate. In one approach, the regulated ramp rate is less for single-level cell programming compared to multi-level cell programming. The target voltage can also be optimized based on the number of bis per cell. ## Claims ### Claim 1 An apparatus, comprising; a first voltage source configured to output a program-inhibit voltage signal to unselected bit lines among a plurality of bit lines in a program operation, the plurality of bit lines are connected to respective NAND strings in a set of NAND strings, and the respective NAND strings comprises memory cells; and a control circuit configured to connect to the first voltage source, the control circuit is configured to: control a ramp up of the program-inhibit voltage signal based on a number of bits per cell to program into selected memory cells of the respective NAND strings. ### Claim 2 (depends on 1) The apparatus of claim 1, wherein: to control the ramp up of the program-inhibit voltage signal, the control circuit is configured to instruct the first voltage source to output the program-inhibit voltage signal with a regulated ramp up rate until the program-inhibit voltage signal reaches a target voltage, after which the program-inhibit voltage signal increases at an unregulated ramp up rate from the target voltage to a program-inhibit voltage. ### Claim 3 (depends on 2) The apparatus of claim 2, wherein: the regulated ramp up rate is an increasing function of the number of bits per cell to program into the selected memory cells. ### Claim 4 (depends on 2) The apparatus of claim 2, wherein: the target voltage is an increasing function of the number of bits per cell to program into the selected memory cells. ### Claim 5 (depends on 2) The apparatus of claim 2, wherein: the regulated ramp up rate is a function of the number of bits per cell to program into the selected memory cells; and the target voltage is a function of the number of bits per cell to program into the selected memory cells. ### Claim 6 (depends on 2) The apparatus of claim 2, wherein: the control circuit is configured to ramp up the program-inhibit voltage signal differently according to whether a single bit is programmed into the selected memory cells or whether multiple bits are programmed into the selected memory cells. ### Claim 7 (depends on 2) The apparatus of claim 2, wherein: the ramp up of the program-inhibit voltage signal occurs prior to application of a program pulse to the selected memory cells. ### Claim 8 (depends on 2) The apparatus of claim 2, wherein: the program-inhibit voltage is independent of the number of bits per cell to program into the selected memory cells. ### Claim 9 (depends on 1) The apparatus of claim 1, further comprising: a second voltage source configured to output a program-enable voltage signal to selected bit lines among the plurality of bit lines in the program operation, wherein the control circuit is configured to connect to the second voltage source, and to control a ramp up of the program-enable voltage signal independent of the number of bits per cell to program into the selected memory cells. ### Claim 10 A method, comprising: increasing a voltage signal from an initial voltage to a program-inhibit voltage in a program operation for memory cells, the memory cells are connected to respective bit lines; and connecting the voltage signal to the respective bit lines, the increasing of the voltage signal is different according to whether the memory cells are programmed to a single bit per cell or to multiple bits per cell. ### Claim 11 (depends on 10) The method of claim 10, wherein: the increasing of the voltage signal is slower when the memory cells are programmed to the single bit per cell than when the memory cells are programmed to the multiple bits per cell. ### Claim 12 (depends on 10) The method of claim 10, wherein: the voltage signal is increased from the initial voltage to a target voltage at a regulated rate and from the target voltage to the program-inhibit voltage at an unregulated rate; and the regulated rate is less when the memory cells are programmed to the single bit per cell than when the memory cells are programmed to the multiple bits per cell. ### Claim 13 (depends on 12) The method of claim 12, wherein: the target voltage is greater when the memory cells are programmed to the single bit per cell than when the memory cells are programmed to the multiple bits per cell. ### Claim 14 (depends on 10) The method of claim 10, wherein: the voltage signal is increased from the initial voltage to a target voltage at a regulated rate and from the target voltage to the program-inhibit voltage at an unregulated rate; and the target voltage is greater when the memory cells are programmed to the single bit per cell than when the memory cells are programmed to the multiple bits per cell. ### Claim 15 (depends on 10) The method of claim 10, wherein: the voltage signal remains at the program-inhibit voltage during application of a program voltage to the memory cells. ### Claim 16 An apparatus, comprising: a set of memory cells connected to a selected word line, each memory cell is arranged in a respective NAND string of a set of NAND strings; a set of bit lines, each bit line is connected to a respective NAND string in the set of NAND strings; and a first voltage source configured to apply a program-inhibit voltage signal to selected bit lines in the set of bit lines, the first voltage source is configured to increase the program-inhibit voltage signal from an initial voltage to a program-inhibit voltage and, when a program pulse is applied to the selected word line in a program operation, to maintain the program-inhibit voltage signal at the program-inhibit voltage, the increasing of the program-inhibit voltage signal is a function of a number of bits per cell to be stored in the set of memory cells in the program operation. ### Claim 17 (depends on 16) The apparatus of claim 16, wherein: to increase the program-inhibit voltage signal from the initial voltage to the program-inhibit voltage, the first voltage source is configured to increase the program-inhibit voltage signal from the initial voltage to a target voltage at a rate which is a function of the number of bits per cell to be stored in the set of memory cells in the program operation, and to then increase the program-inhibit voltage signal from the target voltage to the program-inhibit voltage. ### Claim 18 (depends on 17) The apparatus of claim 17, wherein: the rate at which the program-inhibit voltage signal is increased from the initial voltage to the target voltage is a regulated rate; and the increase of the program-inhibit voltage signal from the target voltage to the program-inhibit voltage is at an unregulated rate. ### Claim 19 (depends on 16) The apparatus of claim 16, wherein: to increase the program-inhibit voltage signal from the initial voltage to the program-inhibit voltage, the first voltage source is configured to increase the program-inhibit voltage signal from the initial voltage to a target voltage which is a function of the number of bits per cell to be stored in the set of memory cells in the program operation, and to then increase the program-inhibit voltage signal from the target voltage to the program-inhibit voltage. ### Claim 20 (depends on 19) The apparatus of claim 19, wherein: the first voltage source is configured to increase the program-inhibit voltage signal from the initial voltage to the target voltage at a rate which is a function of the number of bits per cell to be stored in the set of memory cells in the program operation.