# US 2023/0056747 A1 · Methods for manufacturing semiconductor structures and semiconductor structures

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- Number: US 2023/0056747 A1
- Document ID: US20230056747A1
- Status: Published application
- Kind: A1
- Application number: 17/428,058
- Filed: 2021-02-08
- Published: 2023-02-23
- Earliest claimed: 2020-02-24
- Assignees: Changxin Memory Technologies, Inc.
- Applicants: Changxin Memory Technologies, Inc.
- Inventors: Yuan LI
- Web page: https://patentgrep.com/patent/US20230056747A1

## CPC

- H10W 20/033: {in openings in dielectrics}
- H10W 20/081: {by forming openings in the dielectric parts}
- H10W 20/425: {Barrier, adhesion or liner layers}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

An embodiment of the present application relates to the technical field of semiconductors, and discloses a method for manufacturing a semiconductor structure. In this embodiment, the method comprises: providing an insulating substrate (101); depositing an isolation layer (103) on the insulating substrate (101) by a physical vapor deposition process, the isolation layer (103) comprising cobalt atoms and barrier atoms located at grain boundaries of the cobalt atoms; and depositing a copper-containing metal layer (104) on the isolation layer (103).

## Claims

### Claim 1

A method for manufacturing a semiconductor structure, comprising:
providing an insulating substrate;
depositing an isolation layer on the insulating substrate by a physical vapor deposition process, the isolation layer comprising cobalt atoms and barrier atoms located at grain boundaries of the cobalt atoms; and
depositing a copper-containing metal layer on the isolation layer.

### Claim 2 (depends on 1)

The method for manufacturing a semiconductor structure according to claim 1, wherein a groove is formed on the insulating substrate, and the process of depositing an isolation layer on the insulating substrate comprises:
depositing the isolation layer on the insulating substrate and on the bottom and the sidewalls of the groove.

### Claim 3 (depends on 1)

The method for manufacturing a semiconductor structure according to claim 1, wherein the isolation layer is made of a cobalt-tungsten alloy, and the barrier atoms are tungsten atoms.

### Claim 4 (depends on 3)

The method for manufacturing a semiconductor structure according to claim 3, wherein the content of tungsten in the cobalt-tungsten alloy is from 0.1 at% to 3.5 at%.

### Claim 5 (depends on 4)

The method for manufacturing a semiconductor structure according to claim 4, wherein the temperature for depositing the isolation layer is from 150° C. to 350° C.

### Claim 6 (depends on 5)

The method for manufacturing a semiconductor structure according to claim 5, wherein the process of depositing a copper-containing metal layer on the isolation layer comprises:
cooling the isolation layer to a temperature of from 10° C. to 30° C., and depositing a copper-containing metal layer at a temperature of from 10° C. to 30° C.

### Claim 7 (depends on 4)

The method for manufacturing a semiconductor structure according to claim 4, wherein the flow rate of argon in the preparation environment for depositing the isolation layer is from 10 sccm to 35 sccm.

### Claim 8 (depends on 2)

The method for manufacturing a semiconductor structure according to claim 2, wherein, before depositing an isolation layer, further comprising:
pre-cleaning the bottom and the sidewalls of the groove.

### Claim 9 (depends on 1)

The method for manufacturing a semiconductor structure according to claim 1, wherein the pressure in the preparation environment for depositing the isolation layer is from 0.6 mtorr to 2 mtorr.

### Claim 10 (depends on 1)

The method for manufacturing a semiconductor structure according to claim 1, wherein the thickness of the isolation layer is from 5 nm to 20 nm.

### Claim 11 (depends on 1)

A semiconductor structure, which is prepared according to the method for manufacturing a semiconductor structure according to claim 1.