# US 2023/0056699 A1 · Loop driven region based frontend translation control for performant and secure data-space guided micro-sequencing > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2023/0056699 A1 - Document ID: US20230056699A1 - Status: Published application - Kind: A1 - Application number: 17/409,090 - Filed: 2021-08-23 - Published: 2023-02-23 - Earliest claimed: 2021-08-23 - Assignees: Intel Corporation - Applicants: Intel Corporation - Inventors: Kameswar Subramaniam; Christopher Russell - Web page: https://patentgrep.com/patent/US20230056699A1 ## CPC - G06F 9/3017: {Runtime instruction translation, e.g. macros} - G06F 15/78: comprising a single central processing unit - G06F 9/30145: {Instruction analysis, e.g. decoding, instruction word fields} - G06F 9/30181: {Instruction operation extension or modification} - G06F 9/30185: {according to one or more bits in the instruction, e.g. prefix, sub-opcode} - G06F 9/325: {for loops, e.g. loop detection or loop counter} - G06F 9/3818: {Decoding for concurrent execution} - G06F 9/3836: {Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution} - G06F 9/3844: {using dynamic branch prediction, e.g. using branch history tables} - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract Methods and apparatus relating to loop driven region based frontend translation control for performant and secure data-space guided micro-sequencing are described. In an embodiment, Data-space Translation Logic (DTL) circuitry receives a static input and a dynamic input and generates one or more outputs based at least in part on the static input and the dynamic input. A frontend counter generates a count value for the dynamic input based at least in part on an incremented/decremented counter value and a next counter value from the DTL circuitry. The DTL circuitry is capable to receive a new dynamic input prior to consumption of the one or more outputs. Other embodiments are also disclosed and claimed. ## Claims ### Claim 1 An apparatus comprising: Data-space Translation Logic (DTL) circuitry to receive a static input and a dynamic input and to generate one or more outputs based at least in part on the static input and the dynamic input; and a frontend counter to generate a count value for the dynamic input based at least in part on an incremented/decremented counter value and a next counter value from the DTL circuitry, wherein the DTL circuitry is capable to receive a new dynamic input prior to consumption of the one or more outputs. ### Claim 2 (depends on 1) The apparatus of claim 1, wherein the DTL circuitry is to cause a selection between the incremented/decremented counter value and the next counter value. ### Claim 3 (depends on 2) The apparatus of claim 2, wherein the selection between the incremented/decremented counter value and the next counter value is to allow for skipping of an iteration or a code block region. ### Claim 4 (depends on 1) The apparatus of claim 1, wherein the DTL circuitry is to generate the one or more outputs prior to commencement of speculation operations in a processor. ### Claim 5 (depends on 4) The apparatus of claim 4, wherein a frontend of the processor comprises the DTL circuitry. ### Claim 6 (depends on 1) The apparatus of claim 1, wherein the DTL circuitry comprises a Programmable Logic Array (PLA). ### Claim 7 (depends on 1) The apparatus of claim 1, further comprising a Jump Execution Unit (JEU) to send data from a register file for the dynamic input of the DTL circuitry. ### Claim 8 (depends on 7) The apparatus of claim 7 wherein the JEU is to block data associated with a mispredicted path to be sent for the dynamic input of the DTL circuitry. ### Claim 9 (depends on 1) The apparatus of claim 1, wherein the one or more outputs comprise one or more of: a frontend branch hint, an immediate value, and a micro-operation instruction pointer. ### Claim 10 (depends on 1) The apparatus of claim 1, wherein the DTL circuitry is to atomically program the one or more outputs comprising: a frontend branch hint, an immediate value, and a micro-operation instruction pointer. ### Claim 11 (depends on 1) The apparatus of claim 1, wherein the static input is to indicate a mode of operation for the DTL circuitry. ### Claim 12 (depends on 1) The apparatus of claim 1, wherein the dynamic input is to change for each instruction. ### Claim 13 (depends on 1) The apparatus of claim 1, wherein the dynamic input is to be provided based at least in part on an operand of an instruction. ### Claim 14 (depends on 1) The apparatus of claim 1, wherein a plurality of processor cores of the processor are to share the DTL circuitry. ### Claim 15 An apparatus comprising: Data-space Translation Logic (DTL) circuitry to receive a static input and a dynamic input and to generate one or more outputs based at least in part on the static input and the dynamic input; a frontend counter to generate a count value for the dynamic input based at least in part on an incremented/decremented counter value and a next counter value from the DTL circuitry; decode circuitry to decode an instruction having a field for an operand value; and execution circuitry to execute the decoded instruction to provide the dynamic input based at least in part on the operand value. ### Claim 16 (depends on 15) The apparatus of claim 15, wherein the DTL circuitry is capable to receive a new dynamic input prior to consumption of the one or more outputs. ### Claim 17 (depends on 15) The apparatus of claim 15, wherein the DTL circuitry is to cause a selection between the incremented/decremented counter value and the next counter value. ### Claim 18 (depends on 17) The apparatus of claim 17, wherein the selection between the incremented/decremented counter value and the next counter value is to allow for skipping of an iteration or a code block region. ### Claim 19 (depends on 15) The apparatus of claim 15, wherein the DTL circuitry is to generate the one or more outputs prior to commencement of speculation operations in a processor. ### Claim 20 (depends on 19) The apparatus of claim 19, wherein a frontend of the processor comprises the DTL circuitry. ### Claim 21 (depends on 15) The apparatus of claim 15, further comprising a Jump Execution Unit (JEU) to send data from a register file for the dynamic input of the DTL circuitry. ### Claim 22 (depends on 15) The apparatus of claim 15, wherein the one or more outputs comprise one or more of: a frontend branch hint, an immediate value, and a micro-operation instruction pointer. ### Claim 23 One or more non-transitory computer-readable media comprising one or more instructions that when executed on a processor configure the processor to perform one or more operations to cause: Data-space Translation Logic (DTL) circuitry to receive a static input and a dynamic input and to generate one or more outputs based at least in part on the static input and the dynamic input; a frontend counter to generate a count value for the dynamic input based at least in part on an incremented/decremented counter value and a next counter value from the DTL circuitry; decode circuitry to decode an instruction having a field for an operand value; and execution circuitry to execute the decoded instruction to provide the dynamic input based at least in part on the operand value. ### Claim 24 (depends on 23) The one or more computer-readable media of claim 23, further comprising one or more instructions that when executed on the at least one processor configure the at least one processor to perform one or more operations to cause the DTL circuitry to receive a new dynamic input prior to consumption of the one or more outputs. ### Claim 25 (depends on 23) The one or more computer-readable media of claim 23, further comprising one or more instructions that when executed on the at least one processor configure the at least one processor to perform one or more operations to cause the DTL circuitry to effect a selection between the incremented/decremented counter value and the next counter value.