# US 2023/0056686 A1 · Memory device for correcting pulse duty and memory system including the same

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- Number: US 2023/0056686 A1
- Document ID: US20230056686A1
- Status: Published application
- Kind: A1
- Application number: 17/569,144
- Filed: 2022-01-05
- Published: 2023-02-23
- Earliest claimed: 2021-08-20
- Assignees: SK hynix Inc.
- Applicants: SK hynix Inc.
- Inventors: Jaehyeong HONG; In Seok KONG; Gwan Woo KIM; Jae Young PARK; Kwan Su SHON; Soon Sung AN; Daeho YANG; Sung Hwa OK; Junseo JANG; Yo Han JEONG; Eun Ji CHOI
- Web page: https://patentgrep.com/patent/US20230056686A1

## CPC

- G11C 29/4401: {for self repair}
- G11C 7/222: {Clock generating, synchronizing or distributing circuits within memory device}
- G11C 29/023: {in clock generator or timing circuitry}
- G11C 29/028: {with adaption or trimming of parameters}
- G11C 29/12015: {comprising clock generation or timing circuitry}
- H03K 5/15066: {using bistable devices (H03K5/15093 takes precedence)}
- H03K 5/1565: {the output pulses having a constant duty cycle}
- H03K 19/1774: {for global signals, e.g. clock, reset}
- H03K 19/20: characterised by logic function, e.g. AND, OR, NOR, NOT circuits (H03K19/003 - H03K19/01 take precedence)
- G11C 2029/0411: {Online error correction}
- G11C 2207/2254: Calibration
- Y02D 10/00: Energy efficient computing, e.g. low power processors, power management or thermal management
- G11C: STATIC STORES (semiconductor memory devices H10B)
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)
- Y02D: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE

## Abstract

The present disclosure relates to a memory device for correcting a pulse duty ratio and a memory system including the same, and relates to a memory device which corrects the duty ratio of a primary pulse of a memory device control signal, and a memory system including the same.

## Claims

### Claim 1

A memory system comprising:
a memory device including a plurality of memory blocks and a primary pulse correction module; and
a controller configured to transmit a control signal for controlling the memory device,
wherein the primary pulse correction module includes:
a reset signal generation circuit configured to generate a reset signal on the basis of the control signal;
a primary pulse detection circuit configured to output a detection signal by detecting a primary pulse of the control signal on the basis of the reset signal; and
a corrected primary pulse output circuit configured to correct the primary pulse on the basis of the detection signal.

### Claim 2 (depends on 1)

The memory system according to claim 1, wherein the control signal is one of a data strobe signal and a read enable signal.

### Claim 3 (depends on 2)

The memory system according to claim 2, wherein the reset signal generation circuit is further configured to change a logic level of the reset signal when a preamble period of the control signal starts.

### Claim 4 (depends on 3)

The memory system according to claim 3, wherein the reset signal generation circuit comprises a plurality of NAND gates, a plurality of inverters and at least one flip-flop.

### Claim 5 (depends on 2)

The memory system according to claim 2, wherein the primary pulse detection circuit outputs the detection signal by detecting that the preamble period of the control signal ends and a logic level of the control signal is changed from a logic low level to a logic high level.

### Claim 6 (depends on 5)

The memory system according to claim 5, wherein the primary pulse detection circuit comprises at least one NAND gate, at least one inverter and at least one flip-flop.

### Claim 7 (depends on 5)

The memory system according to claim 5, wherein the detection signal comprises a first detection signal and a second detection signal which is an inverted signal of the first detection signal.

### Claim 8 (depends on 7)

The memory system according to claim 7, wherein:
the control signal comprises a first control signal and a second control signal which is an inverted signal of the first control signal, and
the corrected primary pulse output circuit includes:
a first corrected primary pulse output circuit configured to output a first corrected primary pulse by correcting a duty ratio of a primary pulse of the first control signal on the basis of the first control signal and the first detection signal; and
a second corrected primary pulse output circuit configured to output a second corrected primary pulse by correcting a duty ratio of a primary pulse of the second control signal on the basis of the second control signal and the second detection signal.

### Claim 9 (depends on 8)

The memory system according to claim 8, wherein:
the first corrected primary pulse output circuit includes:
a first PMOS transistor and a first NMOS transistor both configured to receive the first control signal;
a second PMOS transistor configured to receive a first duty correction signal; and
a second NMOS transistor configured to receive a second duty correction signal, and
wherein the second corrected primary pulse output circuit includes:
a third PMOS transistor and a third NMOS transistor both configured to receive the second control signal;
a fourth PMOS transistor configured to receive a third duty correction signal; and
a fourth NMOS transistor configured to receive a fourth duty correction signal.

### Claim 10 (depends on 6)

The memory system according to claim 6, wherein the primary pulse detection circuit further comprises an OR gate which outputs a signal to a reset signal input terminal of the flip-flop by performing an OR logic operation on the chip enable signal and a signal outputted by the reset signal generation circuit.

### Claim 11

A memory device comprising:
a reset signal generation circuit configured to generate a reset signal on the basis of a control signal;
a primary pulse detection circuit configured to output a detection signal by detecting a primary pulse of the control signal on the basis of the reset signal; and
a corrected primary pulse output circuit configured to correct the primary pulse on the basis of the detection signal.

### Claim 12 (depends on 11)

The memory device according to claim 11, wherein the control signal is one of a data strobe signal and a read enable signal.

### Claim 13 (depends on 12)

The memory device according to claim 12, wherein the reset signal generation circuit is further configured to change a logic level of the reset signal when a preamble period of the control signal starts.

### Claim 14 (depends on 13)

The memory device according to claim 13, wherein the reset signal generation circuit comprises a plurality of NAND gates, a plurality of inverters and at least one flip-flop.

### Claim 15 (depends on 12)

The memory device according to claim 12, wherein the primary pulse detection circuit outputs the detection signal by detecting that the preamble period of the control signal ends and a logic level of the control signal is changed from a logic low level to a logic high level.

### Claim 16 (depends on 15)

The memory device according to claim 15, wherein the primary pulse detection circuit comprises at least one NAND gate, at least one inverter and at least one flip-flop.

### Claim 17 (depends on 15)

The memory device according to claim 15, wherein the detection signal comprises a first detection signal and a second detection signal which is an inverted signal of the first detection signal.

### Claim 18 (depends on 17)

The memory device according to claim 17, wherein:
the control signal comprises a first control signal and a second control signal which is an inverted signal of the first control signal, and
the corrected primary pulse output circuit includes:
a first corrected primary pulse output circuit configured to output a first corrected primary pulse by correcting a duty ratio of a primary pulse of the first control signal on the basis of the first control signal and the first detection signal; and
a second corrected primary pulse output circuit configured to output a second corrected primary pulse by correcting a duty ratio of a primary pulse of the second control signal on the basis of the second control signal and the second detection signal.

### Claim 19 (depends on 18)

The memory device according to claim 18, wherein:
the first corrected primary pulse output circuit includes:
a first PMOS transistor and a first NMOS transistor both configured to receive the first control signal;
a second PMOS transistor configured to receive a first duty correction signal; and
a second NMOS transistor configured to receive a second duty correction signal, and
wherein the second corrected primary pulse output circuit includes:
a third PMOS transistor and a third NMOS transistor both configured to receive the second control signal;
a fourth PMOS transistor configured to receive a third duty correction signal; and
a fourth NMOS transistor configured to receive a fourth duty correction signal.

### Claim 20

An operating method of a memory device, the operating method comprising:
detecting a pulse of a data strobe signal immediately after an end of a preamble section of the data strobe signal; and
correcting a duty ratio of the pulse by adjusting a rising edge of the pulse.