# US 2023/0056679 A1 · Memory storage device, an operation method of the memory storage device, test method and electronic device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2023/0056679 A1 - Document ID: US20230056679A1 - Status: Published application - Kind: A1 - Application number: 17/690,163 - Filed: 2022-03-09 - Published: 2023-02-23 - Earliest claimed: 2021-08-17 - Assignees: Samsung Electronics Co., Ltd. - Applicants: Samsung Electronics Co., Ltd. - Inventors: Sung Oh HUH; Jong Kyu CHOI; Soo-Hyeong KIM; Dong Hee KIM; Young San KANG - Web page: https://patentgrep.com/patent/US20230056679A1 ## CPC - G06F 3/0655: {Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices} - G11C 7/20: Memory cell initialisation circuits, e.g. when powering up or down, memory clear, latent image memory - G06F 3/0604: {Improving or facilitating administration, e.g. storage management} - G06F 3/0679: {Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]} - G11C 29/44: Indication or identification of errors, e.g. for repair - G11C 29/48: Arrangements in static stores specially adapted for testing by means external to the store, e.g. using direct memory access [DMA] or using auxiliary access paths - G11C 29/08: Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing - G11C 29/56016: {Apparatus features} - G11C 2029/4402: {Internal storage of test result, quality data, chip identification, repair information} - G11C 2029/5602: {Interface to device under test} - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract A memory storage device that performs real-time monitoring is provided. The memory storage device comprises a memory controller, and a status indicating module/circuit, wherein the memory controller is configured to perform a first a second initialization operation, the first and second initialization operations performed in response to turning-on of the memory storage device, to generate a first status parameter regarding a status of the memory storage device in which the first initialization operation is performed, and to generate a second status parameter regarding the status of the memory storage device in which a second initialization operation is performed. The status indicating circuit includes a first transistor configured to operate on the basis of the first status parameter, a first resistor connected to the first transistor, a second transistor configured to operate on the basis of the second status parameter, and a second resistor connected to the second transistor. ## Claims ### Claim 1 A memory storage device comprising: a memory controller; and a status indicating circuit, wherein the memory controller is configured to perform a first and a second initialization operation in response to turning-on of the memory storage device, to generate a first status parameter regarding a status of the memory storage device in which the first initialization operation is performed, and to generate a second status parameter regarding the status of the memory storage device in which the second initialization operation is performed, the status indicating circuit includes, a first transistor which is configured to operate on the basis of the first status parameter, a first resistor connected to the first transistor, a second transistor which is configured to operate on the basis of the second status parameter, and a second resistor connected to the second transistor. ### Claim 2 (depends on 1) The memory storage device of claim 1, wherein the status indicating circuit is configured to output memory status information indicating resistance values measured on the basis of the first resistor and the second resistor. ### Claim 3 (depends on 2) The memory storage device of claim 2, wherein the memory status information corresponds to a value that is inversely proportional to a sum of a resistance value of the first resistor and a resistance value of the second resistor. ### Claim 4 (depends on 2) The memory storage device of claim 2, wherein the memory status information corresponds to a value that is proportional to the sum of the resistance value of the first resistor and the resistance value of the second resistor. ### Claim 5 (depends on 2) The memory storage device of claim 2, wherein both the first resistor and the second resistor are connected to a common node, and the memory status information is configured to be output from the common node. ### Claim 6 (depends on 2) The memory storage device of claim 2, wherein the first resistor is connected to a node and a first source/drain of the first transistor, and the second resistor is connected to a second source/drain of the first transistor and a first source/drain of the second transistor. ### Claim 7 (depends on 1) The memory storage device of claim 1, wherein the memory controller is configured to perform a third initialization operation different from the first and second initialization operations, and to generate a third status parameter regarding the status of the memory storage device in which the third initialization operation is performed, and the status indicating circuit includes a third transistor that is configured to operate on the basis of the third status parameter, and a third resistor connected to the third transistor. ### Claim 8 (depends on 7) The memory storage device of claim 7, wherein the first resistor, the second resistor, and the third resistor have different resistance values from each other. ### Claim 9 (depends on 1) The memory storage device of claim 1, wherein the status indicating circuit is placed inside the memory controller. ### Claim 10 (depends on 1) The memory storage device of claim 1, wherein the status indicating circuit is placed separately from the memory controller. ### Claim 11 (depends on 1) The memory storage device of claim 1, further comprising: a memory device configured to be controlled by the memory controller, wherein the status indicating circuit is placed inside the memory device. ### Claim 12 An operation method of a memory storage device including a status indicating circuit, the operation method comprising: performing a first initialization operation on the memory storage device; toggling a first status parameter at a first time, on the basis of a first status of the memory storage device in which the first initialization operation is performed; performing a second initialization operation on the memory storage device; toggling a second status parameter at a second time following the first time, on the basis of a second status of the memory storage device in which the second initialization operation is performed; providing the first status parameter and the second status parameter to the status indicating circuit; and switching a first resistor to a second resistor on the basis of toggling of the first status parameter, and switching the second resistor to a third resistor on the basis of toggling of the second status parameter, by the status indicating circuit, wherein the first to third resistors are different from each other. ### Claim 13 (depends on 12) The operation method of the memory storage device of claim 12, wherein toggling of the first status parameter on the basis of the first status of the memory storage device in which the first initialization operation is performed includes, toggling the first status parameter in response to the first status of the memory storage device being normal, and not toggling the first status parameter when the first status of the memory storage device being abnormal. ### Claim 14 (depends on 13) The operation method of the memory storage device of claim 13, further comprising: not changing the first resistor on the basis of non-toggling of the first status parameter by the status indicating circuit. ### Claim 15 (depends on 14) The operation method of the memory storage device of claim 14, further comprising: outputting memory status information including a resistance value of the first resistor in response to the first resistor being maintained. ### Claim 16 (depends on 13) The operation method of the memory storage device of claim 13, further comprising: performing the second initialization operation in response to the toggling of the first status parameter. ### Claim 17 (depends on 12) The operation method of the memory storage device of claim 12, wherein the first resistor is greater than the second resistor and greater than third resistors, and the second resistor is greater than the third resistor. ### Claim 18 (depends on 12) The operation method of the memory storage device of claim 12, further comprising: outputting memory status information including a resistance value of one of the first to third resistors by the status indicating circuit. ### Claim 19 A test method comprising: connecting a memory storage device to a main board; connecting a test apparatus to a test pin connected to the memory storage device; performing, by the memory storage device, a plurality of initialization operations and changing a resistance value connected to the test pin based on performance results of the plurality of initialization operations; and measuring the resistance value and outputting status information of the memory storage device on the basis of the resistance value, by the test apparatus. ### Claim 20 (depends on 19) The test method of claim 19, further comprising: performing debugging of an application processor, a passive element, and a memory storage device connected to the main board, the debugging on the basis of status information of the memory storage device. ### Claim at position 21 21-27. (canceled)