# US 2023/0056640 A1 · Stacked random-access memory devices

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- Number: US 2023/0056640 A1
- Document ID: US20230056640A1
- Status: Published application
- Kind: A1
- Application number: 17/406,558
- Filed: 2021-08-19
- Published: 2023-02-23
- Earliest claimed: 2021-08-19
- Assignees: Intel Corporation
- Applicants: Intel Corporation
- Inventors: Abhishek A. Sharma; Clifford Lu Ong; Van H. Le; Hui Jae Yoo
- Web page: https://patentgrep.com/patent/US20230056640A1

## CPC

- G11C 11/005: {comprising combined but independently operative RAM-ROM, RAM-PROM, RAM-EPROM cells}
- H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
- G11C 5/025: {Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device (geometrical lay-out of the components in integrated circuits, geometrical lay-out of the components in integrated circuits H10D89/10)}
- G11C 11/408: Address circuits
- G11C 11/4087: {Address decoders, e.g. bit - or word line decoders; Multiple line decoders}
- G11C 11/412: using field-effect transistors only
- G11C 11/418: Address circuits
- H10B 80/00: Assemblies of multiple devices comprising at least one memory device covered by this subclass
- H10W 20/023: {the interconnections being through-semiconductor vias}
- H10W 80/00: Direct bonding of chips, wafers or substrates
- H10W 90/00: Package configurations
- H10W 99/00: Subject matter not provided for in other groups of this subclass
- H10B 10/18: {Peripheral circuit regions}
- H10B 12/50: {Peripheral circuit region structures}
- H10D 89/10: Integrated device layouts
- H10W 90/26: the stacked chips being of the same size without any chips being laterally offset, e.g. chip stacks having a rectangular shape
- G11C: STATIC STORES (semiconductor memory devices H10B)
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10B: ELECTRONIC MEMORY DEVICES
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

Described herein are stacked memory devices that include some peripheral devices for controlling the memory in a separate layer from one or more memory arrays. The layers of the memory device are connected together using vias, which transfer power and data between the layers. In some examples, a portion of the peripheral devices are included in a memory layer, and another portion are included in a peripheral device layer. Multiple layers of memory arrays and/or peripheral devices may be included, e.g., one peripheral device layer may control multiple layers of memory arrays, or different layers of memory arrays may have dedicated peripheral device layers. Different types of memory arrays, such as DRAM or SRAM, may be included.

## Claims

### Claim 1

A memory device comprising:
a memory array comprising a plurality of bitcells;
a plurality of peripheral devices coupled to the memory array, the plurality of peripheral devices in a first layer of the memory device, and the memory array in a second layer of the memory device, the second layer over the first layer; and
a via coupling the first layer to the second layer.

### Claim 2 (depends on 1)

The memory device of claim 1, wherein a first via extends along a first side of the memory array, and a second via extends along a second side of the memory array opposite the first side.

### Claim 3 (depends on 2)

The memory device of claim 2, wherein the first via has a first width, and the second via has a second width larger than the first width.

### Claim 4 (depends on 1)

The memory device of claim 1, further comprising a second memory array, the second memory array in a third layer of the memory device, the third layer over the second layer.

### Claim 5 (depends on 4)

The memory device of claim 4, wherein a second via extends from the first layer to the third layer.

### Claim 6 (depends on 5)

The memory device of claim 5, wherein the second via couples one of the plurality of peripheral devices to the second memory array, and a width of the second via decreases monotonically from the third layer to the first layer.

### Claim 7 (depends on 5)

The memory device of claim 5, wherein the second via couples one of the plurality of peripheral devices to the second memory array, and a width of the second via increases monotonically from the third layer to the first layer.

### Claim 8 (depends on 4)

The memory device of claim 4, further comprising a second plurality of peripheral devices in a fourth layer, the fourth layer between the second layer and the third layer.

### Claim 9 (depends on 1)

The memory device of claim 1, further comprising a bonding material between the first layer and the second layer, the via extending through the bonding material.

### Claim 10 (depends on 1)

The memory device of claim 1, wherein the plurality of peripheral devices comprises at least one of a self-test block, a voltage block, a repeater, mid-logic, and input and output circuitry.

### Claim 11

A memory device comprising:
a first layer comprising input and output (I/O) circuitry;
a second layer comprising a repeater; and
a third layer comprising at least one memory array, the second layer between the first layer and the third layer.

### Claim 12 (depends on 11)

The memory device of claim 11, wherein transistor in the I/O circuitry in the first layer has a first gate height and a first channel length, and a transistor in a memory cell in the third layer has a second gate height less than the first gate height, and a second channel length less than the first channel length.

### Claim 13 (depends on 11)

The memory device of claim 11, wherein the first layer further comprises a voltage block, the voltage block comprising at least one capacitor.

### Claim 14 (depends on 11)

The memory device of claim 11, the second layer further comprising a voltage block, the voltage block comprising at least one capacitor.

### Claim 15 (depends on 11)

The memory device of claim 11, wherein the second layer further comprises mid-logic, the mid-logic comprising an address decoder.

### Claim 16 (depends on 15)

The memory device of claim 15, wherein at least a portion of a mid-logic block in the second layer is aligned with at least a portion of a memory array in the third layer.

### Claim 17 (depends on 11)

The memory device of claim 11, wherein the third layer further comprises mid-logic, the mid-logic comprising an address decoder.

### Claim 18

An integrated circuit (IC) device comprising:
a processing unit; and
a memory structure coupled to the processing unit, the memory structure comprising:
a memory layer comprising a memory array, the memory array comprising a plurality of bitcells; and
a peripheral device layer comprising peripheral devices, at least one peripheral device coupled to the memory array, and at least one peripheral device coupled to the processing unit.

### Claim 19 (depends on 18)

The IC device of claim 18, wherein the memory structure comprises a via coupling the peripheral device layer to the memory structure.

### Claim 20 (depends on 18)

The IC device of claim 18, wherein the peripheral device layer comprises a voltage block, at least one repeater.