# US 2023/0056623 A1 · Semiconductor structure and method for preparing same > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2023/0056623 A1 - Document ID: US20230056623A1 - Status: Published application - Kind: A1 - Application number: 17/658,037 - Filed: 2022-04-05 - Published: 2023-02-23 - Earliest claimed: 2021-08-19 - Assignees: Changxin Memory Technologies, Inc. - Applicants: Changxin Memory Technologies, Inc. - Inventors: CHIH-CHENG LIU - Web page: https://patentgrep.com/patent/US20230056623A1 ## CPC - H10W 72/019: {of bond pads} - H10P 74/273: {Interconnections for measuring or testing, e.g. probe pads} - H10W 72/90: Bond pads, in general - H10W 70/05: of insulating or insulated package substrates, or of interposers, or of redistribution layers (manufacture or treatment of leadframes H10W70/04) - H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40) - H10W 70/65: Shapes or dispositions of interconnections - H10W 70/66: Conductive materials thereof - H10W 72/922: {Bond pads being integral with underlying chip-level interconnections} - H10W 72/931: {Shapes of bond pads} - H10W 72/932: {Plan-view shape, i.e. in top view} - H10W 72/934: {Cross-sectional shape, i.e. in side view} - H10W 72/942: {relative to underlying supporting features, e.g. bond pads, RDLs or vias} - H10W 72/967: {Multiple bond pads having different functions} - H10W 72/981: {Auxiliary members, e.g. spacers} - H10W 72/983: {Reinforcing structures, e.g. collars} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 - H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10 ## Abstract A semiconductor structure includes: a substrate, a conductive pattern layer, a support layer and a re-distribution layer. The conductive pattern layer is arranged on the substrate. The support layer covers the conductive pattern layer and is provided with a via hole. The re-distribution layer is arranged on the support, and the re-distribution layer includes a test pad at least located in the via hole. The test pad includes a plurality of test contact portions and a plurality of recesses that are arranged alternately and connected mutually, and the recess is in corresponding contact with a portion of the conductive pattern layer in the via hole. ## Claims ### Claim 1 A semiconductor structure, comprising: a substrate; a conductive pattern layer, arranged on the substrate; a support layer, covering the conductive pattern layer and provided with a via hole; and a re-distribution layer, arranged on the support layer; the re-distribution layer comprising: a test pad at least located in the via hole; the test pad comprising a plurality of test contact portions and a plurality of recesses that are arranged alternately and connected mutually, wherein the recess is in corresponding contact with a portion of the conductive pattern layer in the via hole. ### Claim 2 (depends on 1) The semiconductor structure according to claim 1, wherein a gap between tops of two adjacent ones of the test contact portions is smaller than a gap between bottoms of the two adjacent ones of the test contact portions; or tops of two adjacent ones of the test contact portions are in contact with each other. ### Claim 3 (depends on 1) The semiconductor structure according to claim 1, further comprising: a plurality of spacers in the via hole; wherein an interval is provided between any two adjacent ones of the spacers; and the test pad covers the spacers and the intervals, the test contact portion is correspondingly located on a surface, facing away from the substrate, of the spacer, and the recess is correspondingly located in the interval. ### Claim 4 (depends on 3) The semiconductor structure according to claim 3, wherein the spacers comprise strip-shaped spacers; a plurality of strip-shaped spacers are arranged in parallel at intervals, and two ends, in a length direction, of the strip-shaped spacer are respectively connected to side walls of the via hole; or the spacers comprise blocky spacers; and a plurality of blocky spacers are distributed in an array. ### Claim 5 (depends on 4) The semiconductor structure according to claim 4, wherein a width value of an orthographic projection of the spacer on the substrate ranges from 6 μm to 10 μm. ### Claim 6 (depends on 1) The semiconductor structure according to claim 1, further comprising: a spacer that is located in the via hole and hollowed out as a grid; and the test pad covers the spacer, the test contact portion is correspondingly located on a surface, facing away from the substrate, of the spacer, and the recess is correspondingly located in a hollow-out area of the spacer. ### Claim 7 (depends on 3) The semiconductor structure according to claim 3, wherein the surface, facing away from the substrate, of the spacer is flush with a surface, facing away from the substrate, of the support layer. ### Claim 8 (depends on 3) The semiconductor structure according to claim 3, wherein a material of the spacer or of the support layer comprises at least one of silicon oxide, silicon nitride, or an organic insulating material. ### Claim 9 (depends on 1) The semiconductor structure according to claim 1, wherein a shape of an orthographic projection of the via hole on the substrate comprises: a rectangle, a square, a circle, or an ellipse; and a minimum size of the orthographic projection of the via hole on the substrate is greater than or equal to 10 μm. ### Claim 10 (depends on 1) The semiconductor structure according to claim 1, wherein a maximum size of an orthographic projection of the test pad on the substrate is greater than or equal to 50 μm. ### Claim 11 (depends on 1) The semiconductor structure according to claim 1, wherein a distance from a surface, facing away from the conductive pattern layer, of the test contact portion to the conductive pattern layer is greater than or equal to 5 μm. ### Claim 12 (depends on 1) The semiconductor structure according to claim 1, wherein the re-distribution layer further comprises a bonding pad coupled to the test pad; and an orthographic projection of the bonding pad on the substrate is located outside an orthographic projection of the test pad on the substrate. ### Claim 13 (depends on 6) The semiconductor structure according to claim 6, wherein the surface, facing away from the substrate, of the spacer is flush with a surface, facing away from the substrate, of the support layer. ### Claim 14 (depends on 6) The semiconductor structure according to claim 6, wherein a material of the spacer or of the support layer comprises at least one of silicon oxide, silicon nitride, or an organic insulating material. ### Claim 15 A method for preparing a semiconductor structure, comprising: providing a substrate, and forming a conductive pattern layer on the substrate; forming a support layer on the conductive pattern layer, and forming a via hole in the support layer; and forming a re-distribution layer on the support layer, wherein the re-distribution layer comprises a test pad that is at least located in the via hole, the test pad comprising a plurality of test contact portions and a plurality of recesses that are arranged alternately and connected mutually, and wherein the recess is in corresponding contact with a portion of the conductive pattern layer in the via hole. ### Claim 16 (depends on 15) The method for preparing a semiconductor structure according to claim 15, wherein the method, before forming the re-distribution layer on the support layer, further comprises: forming a plurality of spacers in the via hole, wherein an interval is provided between any two adjacent ones of the spacers; and said forming a re-distribution layer on the support layer comprises: forming the test contact portion at least on a surface, facing away from the substrate, of the spacer, and forming the recess in the interval. ### Claim 17 (depends on 16) The method for preparing a semiconductor structure according to claim 16, wherein said forming a plurality of spacers in the via hole comprises: forming a plurality of strip-shaped spacers that are arranged in parallel at intervals in the via hole, wherein two ends, in a length direction, of the strip-shaped spacer are respectively connected to side walls of the via hole; or forming in the via hole a plurality of blocky spacers that are distributed in an array. ### Claim 18 (depends on 15) The method for preparing a semiconductor structure according to claim 15, wherein the method, before forming the re-distribution layer on the support layer, further comprises: forming in the via hole a spacer that is hollowed out as a grid; and said forming a re-distribution layer on the support layer comprises: forming the test contact portion at least on a surface, facing away from the substrate, of the spacer, and forming the recess in a hollow-out area of the spacer. ### Claim 19 (depends on 16) The method for preparing a semiconductor structure according to claim 16, wherein the via hole and the spacer are formed by one patterning process. ### Claim 20 (depends on 15) The method for preparing a semiconductor structure according to claim 15, wherein said forming a re-distribution layer on the support layer further comprises: forming a bonding pad on the support layer, wherein an orthographic projection of the bonding pad on the substrate is located outside an orthographic projection of the test pad on the substrate.