# US 2023/0056586 A1 · Method for identifying address of slave devices, system, and device applying the method > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2023/0056586 A1 - Document ID: US20230056586A1 - Status: Published application - Kind: A1 - Application number: 17/510,859 - Filed: 2021-10-26 - Published: 2023-02-23 - Earliest claimed: 2021-08-23 - Assignees: Fulian Precision Electronics (Tianjin) Co., LTD. - Applicants: Fulian Precision Electronics (Tianjin) Co., LTD. - Inventors: XIAO-LONG ZHOU - Web page: https://patentgrep.com/patent/US20230056586A1 ## CPC - G06F 13/14: Handling requests for interconnection or transfer - G06F 1/26: Power supply means, e.g. regulation thereof (for memories G11C) - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract In a method and system for identifying addresses of slave devices, the system includes a main board, slave devices, and a power source. The main board is electrically connected to the slave devices and a delay unit is set in each slave device. An output terminal of the delay unit is electrically connected to the main board. The delay unit outputs a delay signal to the main board when first powered on, the main board receives the delay signal, computes a delay time of the delay signal, and by reference to a preset table identifies the slave device based on the specific delay time. Occupation of input and output I/O pins is reduced, a device for identifying addresses of slave devices is also disclosed. ## Claims ### Claim 1 A system for identifying addresses of slave devices, the system comprises: a main board; a plurality of slave devices; and a power source; wherein the power source is electrically connected to the main board and the slave devices, the main board is electrically connected to the slave devices, the power source powers the main board and the slave devices, a delay unit is set in each of the plurality of slave devices, an output terminal of the delay unit is electrically connected to the main board and outputs a delay signal to the main board, and the main board receives the delay signal, computes a delay time of the delay signal, and identifies the slave device based on the delay time. ### Claim 2 (depends on 1) The system of claim 1, wherein a delay capacitor is set in each delay unit; the delay capacitor is configured to adjust the delay time. ### Claim 3 (depends on 2) The system of claim 2, wherein the plurality of slave devices comprises a first slave device and a second slave device; the delay unit at least comprises a first delay unit and a second delay unit; the first delay unit is set in the first slave device, and the second delay unit is set in the second slave device; the first delay unit and the second delay unit are electrically connected to the main board respectively; and delay capacitor in the first delay unit is different from delay capacitor in the second delay unit. ### Claim 4 (depends on 3) The system of claim 3, wherein the system pre-stores a mapped table between the delay times and address information of the slave devices; and the main board obtains the address information of the slave device based on the delay time and identifies the slave device based on the address information. ### Claim 5 (depends on 4) The system of claim 4, wherein the first delay unit is configured to output a first delay signal to the main board, and the second delay unit is configured to output a second delay signal to the main board; the main board receives the first delay signal and computes a first delay time of the first delay signal; the main board receives the second delay signal and computes a second delay time of the second delay signal; the main board obtains a first address information from the mapped table based on the first delay time and obtains a second address information from the mapped table; and the main board identifies the first slave device based on the first address information and identifies the second slave device based on the second address information. ### Claim 6 A method for identifying addresses of slave devices, used in a system for identifying addresses of slave devices, the system comprises a main board, a plurality of slave devices, and a power source, the power source is electrically connected to the main board and the slave devices, the main board is electrically connected to the slave devices, a delay unit is set in each of the plurality of slave devices; an output terminal of the delay unit is electrically connected to the main board; the method comprises: powering on the system; starting to count time and receiving a delay signal outputted by the delay unit by the mainboard; and computing a delay time of the delay signal by the main board and identifying the slave device based on the delay time. ### Claim 7 (depends on 6) The method of claim 6, wherein a delay capacitor is set in each delay unit; the method further comprises: the delay time is adjusted by changing a capacitance of the delay capacitor. ### Claim 8 (depends on 7) The method of claim 7, wherein the system pre-stores a mapped table between the delay times and address information of the slave devices, the method further comprising: receiving, by the main board, the delay signal and computing the delay time of the delay signal; obtaining, by the main board, the address information of the slave device based on the delay time; and identifying by the main board the slave device based on the address information. ### Claim 9 (depends on 8) The method of claim 8, wherein the plurality of slave devices at least comprises a first slave device and a second slave device; a first delay unit is set in the first slave device and a second delay unit is set in the second slave device; the first delay unit and the second delay unit are electrically connected to the main board respectively; and delay capacitor in the first delay unit is different from delay capacitor in the second delay unit. ### Claim 10 (depends on 9) The method of claim 9, wherein the first delay unit is configured to output a first delay signal to the main board, the second delay unit is configured to output a second delay signal to the main board, the method further comprising: receiving, by the main board, the first delay signal and computing a first delay time of the first delay signal; receiving, by the main board, the second delay signal and computing a second delay time of the second delay signal; obtaining, by the main board a first address information from the mapped table based on the first delay time and obtaining a second address information from the mapped table; and identifying, by the main board the first slave device based on the first address information and identifying the second slave device based on the second address information. ### Claim 11 A device for identifying addresses of slave devices, the device comprises a main board, a plurality of slave devices, and a power source, the power source is electrically connected to the main board and the slave devices, the main board is electrically connected to the slave devices, a delay unit is set in each of the plurality of slave devices; an output terminal of the delay unit is electrically connected to the main board; the device comprises: a storage; and a processor, wherein the storage stores computer programs, and the processor executes the computer programs to implement the following steps: powering on the system; starting to count time, by the main board, and receiving a delay signal outputted by the delay unit; and computing, by the main board, a delay time of the delay signal and identifying the slave device based on the delay time. ### Claim 12 (depends on 11) The device of claim 11, wherein a delay capacitor is set in each delay unit; the delay time is adjusted by changing a capacitance of the delay capacitor. ### Claim 13 (depends on 12) The device of claim 12, wherein the system pre-stores a mapped table between the delay times and address information of the slave devices; the steps of the processor executing the computer programs further comprising: receiving, by the main board, the delay signal and computing the delay time of the delay signal; obtaining, by the main board, the address information of the slave device based on the delay time; and identifying, by the main board, the slave device based on the address information. ### Claim 14 (depends on 13) The device of claim 13, wherein the plurality of slave devices at least comprises a first slave device and a second slave device; a first delay unit is set in the first slave device, and a second delay unit is set in the second slave device; the first delay unit and the second delay unit are electrically connected to the main board respectively; delay capacitor in the first delay unit is different from delay capacitor in the second delay unit. ### Claim 15 (depends on 14) The device of claim 14, wherein the first delay unit is configured to output a first delay signal to the main board; the second delay unit is configured to output a second delay signal to the main board; the steps of the processor executing the computer programs further comprising: receiving, by the main board, the first delay signal, and computing a first delay time of the first delay signal; receiving, by the main board, the second delay signal, and computing a second delay time of the second delay signal; obtaining, by the main board, a first address information from the mapped table based on the first delay time, and obtaining a second address information from the mapped table; and identifying, by the main board, the first slave device based on the first address information and identifying the second slave device based on the second address information.