# US 2023/0056584 A1 · Manufacturing method of semiconductor structure

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- Number: US 2023/0056584 A1
- Document ID: US20230056584A1
- Status: Published application
- Kind: A1
- Application number: 17/439,904
- Filed: 2021-06-22
- Published: 2023-02-23
- Earliest claimed: 2020-12-23
- Assignees: Changxin Memory Technologies, Inc.
- Applicants: Changxin Memory Technologies, Inc.
- Inventors: Jingwen LU
- Web page: https://patentgrep.com/patent/US20230056584A1

## CPC

- H10B 12/482: {Bit lines}
- H10B 12/00: Dynamic random access memory [DRAM] devices
- H10W 10/014: {using trench refilling with dielectric materials, e.g. shallow trench isolations}
- H10W 10/17: formed using trench refilling with dielectric materials, e.g. shallow trench isolations
- H10W 20/435: {Cross-sectional shapes or dispositions of interconnections}
- H10B: ELECTRONIC MEMORY DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

The present application provides a manufacturing method of a semiconductor structure, and relates to the technical field of semiconductors. The manufacturing method includes: providing a substrate; and forming multiple spaced first isolation sidewall structures on the substrate, where first opening regions are formed between adjacent first isolation sidewall structures, and each of the first opening regions is used to expose at least two columns of active regions.

## Claims

### Claim 1

A manufacturing method of a semiconductor structure, comprising:
providing a substrate, wherein the substrate comprises multiple active regions and an isolation structure for isolating each of the active regions; the multiple active regions are arranged in several columns along a first direction;
forming multiple spaced first isolation sidewall structures on the substrate, wherein first opening regions are formed between adjacent first isolation sidewall structures, and each of the first opening regions is used to expose at least two columns of active regions;
forming a conductive layer on the substrate located in the first opening regions, wherein a height of the conductive layer is lower than heights of the first isolation sidewall structures; and
removing part of the conductive layer located in the first opening region to form two spaced bit line structures, wherein the two bit line structures are respectively in contact with one of the two first isolation sidewall structures forming the first opening region.

### Claim 2 (depends on 1)

The manufacturing method of the semiconductor structure according to claim 1, wherein the forming multiple spaced first isolation sidewall structures on the substrate comprises:
sequentially stacking a sacrificial layer and a photoresist layer on the substrate;
patterning the photoresist layer to form multiple second opening regions and multiple shielding regions for isolating each of the second opening regions in the photoresist layer, wherein a projection of each of the shielding regions on the substrate overlaps with at least two columns of active regions;
removing the sacrificial layer located in the second opening regions to retain the sacrificial layer located below the shielding regions, wherein the sacrificial layer located below the shielding regions forms isolation portions, and isolation regions are formed between adjacent isolation portions; and
forming the first isolation sidewall structures in the isolation regions.

### Claim 3 (depends on 2)

The manufacturing method of the semiconductor structure according to claim 2, wherein the forming the first isolation sidewall structures in the isolation regions comprises:
forming a first isolation structure on sidewalls of the isolation regions, bottom walls of the isolation regions and top surfaces of the isolation portions;
forming a first dielectric layer on the first isolation structure, wherein the first dielectric layer fills the isolation regions; and
removing the isolation portions and the first isolation structure and the first dielectric layer on the top surfaces of the isolation portions, and retaining the first isolation structure and the first dielectric layer on the substrate, wherein the retained first isolation structure and first dielectric layer form the first isolation sidewall structures.

### Claim 4 (depends on 3)

The manufacturing method of the semiconductor structure according to claim 3, wherein forming the first isolation structure in the isolation regions comprises:
sequentially stacking a first isolation layer, a second isolation layer and a third isolation layer in the isolation regions, wherein the third isolation layer is in contact with the first dielectric layer;
the first isolation layer and the third isolation layer are made of a same material, and the first isolation layer and the second isolation layer are made of different materials.

### Claim 5 (depends on 4)

The manufacturing method of the semiconductor structure according to claim 4, wherein the sequentially stacking a first isolation layer, a second isolation layer and a third isolation layer in the isolation regions comprises:
forming a first isolation layer in the isolation regions, wherein the first isolation layer covers sidewalls of the isolation portions;
forming a second isolation layer on a sidewall of the first isolation layer, the substrate exposed in the isolation regions and the top surfaces of the isolation portions; and forming a third isolation layer on the second isolation layer.

### Claim 6 (depends on 5)

The manufacturing method of the semiconductor structure according to claim 5, wherein the removing the isolation portions and the first isolation structure and the first dielectric layer on the top surfaces of the isolation portions comprises:
removing the first dielectric layer located on a top surface of the first isolation structure and part of the first dielectric layer located in the isolation regions, such that the first dielectric layer located in the isolation regions forms recesses;
forming a barrier layer in the recesses; and
using the barrier layer as a mask to remove the isolation portions and the first isolation structure on the top surfaces of the isolation portions.

### Claim 7 (depends on 6)

The manufacturing method of the semiconductor structure according to claim 6, wherein depths of the recesses are 1-3 times a thickness of the third isolation layer in contact with the first dielectric layer.

### Claim 8 (depends on 7)

The manufacturing method of the semiconductor structure according to claim 7, wherein the forming a conductive layer on the substrate located in the first opening regions, wherein a height of the conductive layer is lower than heights of the first isolation sidewall structures comprises:
forming a first conductive layer on the substrate located in the first opening regions, wherein a height of the first conductive layer is lower than the heights of the first isolation sidewall structures;
forming a second conductive layer and a third conductive layer on the first conductive layer; and
etching back the second conductive layer and the third conductive layer such that a height of the third conductive layer is lower than the heights of the first isolation sidewall structures, wherein the first conductive layer, the second conductive layer and the third conductive layer form the conductive layer.

### Claim 9 (depends on 8)

The manufacturing method of the semiconductor structure according to claim 8, wherein the removing part of the conductive layer located in the first opening region to form two spaced bit line structures comprises:
forming a second dielectric layer on sidewalls and top surfaces of the first isolation sidewall structures located on an upper part of the conductive layer and on a top surface of the conductive layer; and
using the second dielectric layer as a mask to etch part of the conductive layer located in the first opening regions, so as to form two spaced bit line structures.

### Claim 10 (depends on 9)

The manufacturing method of the semiconductor structure according to claim 9, wherein a thickness of the second dielectric layer is equal to widths of the formed bit line structures.

### Claim 11 (depends on 10)

The manufacturing method of the semiconductor structure according to claim 10, wherein after the removing part of the conductive layer located in the first opening region to form two spaced bit line structures, the method further comprises:
forming a second isolation sidewall structure on a sidewall of each of the bit line structures facing the other bit line structure, wherein the second isolation sidewall structure extends in a direction perpendicular to the substrate.

### Claim 12 (depends on 11)

The manufacturing method of the semiconductor structure according to claim 11, wherein the second isolation sidewall structure comprises a fourth isolation layer, a fifth isolation layer and a sixth isolation layer sequentially formed on the sidewall of the bit line structure;
the fourth isolation layer and the sixth isolation layer are made of a same material, and the fourth isolation layer and the fifth isolation layer are made of different materials.

### Claim 13 (depends on 12)

The manufacturing method of the semiconductor structure according to claim 12, wherein after the forming a second isolation sidewall structure on a sidewall of each of the bit line structures facing the other bit line structure, the method further comprises:
filling the first opening regions with a third dielectric layer, wherein the third dielectric layer extends outside the first opening regions and covers top surfaces of the first isolation sidewall structures, the second isolation sidewall structures and the bit line structures.

### Claim 14 (depends on 13)

The manufacturing method of the semiconductor structure according to claim 13, wherein after the filling the first opening regions with a third dielectric layer, the method further comprises:
planarizing a surface of the third dielectric layer.