# US 2023/0056579 A1 · Apparatus including integrated pads and methods of manufacturing the same

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- Number: US 2023/0056579 A1
- Document ID: US20230056579A1
- Status: Published application
- Kind: A1
- Application number: 17/408,343
- Filed: 2021-08-20
- Published: 2023-02-23
- Earliest claimed: 2021-08-20
- Assignees: Micron Technology, Inc.
- Applicants: Micron Technology, Inc.
- Inventors: Wei Zhou; Thiagarajan Raman
- Web page: https://patentgrep.com/patent/US20230056579A1

## CPC

- H10W 40/228: {the projecting parts being wire-shaped or pin-shaped}
- H10W 74/476: {Organic materials comprising silicon}
- H10W 40/778: {in encapsulations}
- H10W 42/121: {protecting against mechanical damage (H10W76/00, H10W74/00 take precedence)}
- H10W 72/019: {of bond pads}
- H10W 74/01: Manufacture or treatment
- H10W 74/147: {the encapsulations being multilayered}
- H10W 72/9232: {with additional elements interposed between layers}
- H10W 72/965: {Providing thermal transfer}
- H10W 72/967: {Multiple bond pads having different functions}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

Semiconductor devices including electrically-isolated extensions and associated systems and methods are disclosed herein. An electrically-isolated extension may be coupled to a corresponding connection pad that is attached to a surface of a device. The electrically-isolated extensions may extend at least partially through one or more layers at or near the surface and toward a substrate or an inner portion thereof.

## Claims

### Claim 1

An apparatus, comprising:
a semiconductor substrate, wherein the semiconductor substrate corresponds to a semiconductor wafer;
a passivation layer covering a backside of the semiconductor substrate, wherein at least a portion of a surface of the passivation layer comprises a surface of the semiconductor substrate;
a connection pad disposed over the passivation layer of the semiconductor substrate; and
an extension directly coupled to the connection pad and extending from the connection pad into the passivation layer, wherein the extension and the connection pad are electrically isolated from the semiconductor substrate.

### Claim 2 (depends on 1)

The apparatus of claim 1, wherein the extension extends into the passivation layer by a length less than a distance between a surface of the passivation layer and the semiconductor substrate.

### Claim 3 (depends on 1)

The apparatus of claim 1, wherein the extension has a length less than or equal to a thickness of the passivation layer.

### Claim 4 (depends on 3)

The apparatus of claim 3, wherein the passivation layer includes a tetraethyl orthosilicate (TEOS) layer.

### Claim 5 (depends on 1)

The apparatus of claim 1, further comprising:
a barrier layer disposed between the passivation layer and the semiconductor substrate.
wherein
the extension extends at least through the passivation layer to the barrier layer.

### Claim 6 (depends on 5)

The apparatus of claim 5, wherein the extension extends at least partially through the barrier layer.

### Claim 7 (depends on 5)

The apparatus of claim 5, wherein the barrier layer comprises SiN.

### Claim 8 (depends on 1)

The apparatus of claim 1, wherein the connection pad is a first connection pad, and further comprising:
a second connection pad disposed over the passivation layer; and
a through silicon via (TSV) directly coupled to the second connection pad and extending from the second connection pad through the passivation layer and into the semiconductor substrate,
wherein
the extension has a first length less than a second length of the TSV.

### Claim 9 (depends on 1)

The apparatus of claim 1, wherein the extension includes a thermally conductive material and is thermally coupled to the connection pad.

### Claim 10 (depends on 9)

The apparatus of claim 9, wherein the connection pad is a thermal pad configured to provide an external interface for removing thermal energy away from the semiconductor device.

### Claim 11 (depends on 1)

The apparatus of claim 1, wherein:
the connection pad has a first width; and
the extension has a second width less than the first width.

### Claim 12 (depends on 1)

The apparatus of claim 1, wherein the extension is one extension within a set of extensions, extensions in the set of electrically-isolated extensions being:
directly coupled to the connection pad,
separated from each other by at least a separation distance,
covered by the connection pad, and
electrically isolated from the semiconductor substrate.

### Claim 13 (depends on 12)

The apparatus of claim 12, wherein the set of extensions includes at least one cross-linking structure extending between and connected to at least two adjacent extensions of the set.

### Claim 14

A semiconductor device, comprising:
a semiconductor substrate, wherein the semiconductor substrate corresponds to a semiconductor wafer;
active circuitry formed on a frontside of the semiconductor substrate;
an electrical pad over a backside of the semiconductor substrate and electrically coupled to the active circuitry, wherein the electrical pad is configured to provide an external electrical interface for the active circuitry in the semiconductor device;
a thermal pad over the backside to the semiconductor substrate and electrically isolated from the active circuitry and the semiconductor substrate, wherein the thermal pad is configured to provide an external thermal interface for removing thermal energy from the semiconductor device; and
an extension coupled to the thermal pad and extending from the thermal pad and toward an inner portion of the semiconductor substrate, wherein the extension is electrically isolated from the active circuitry and the semiconductor circuitry.

### Claim 15 (depends on 14)

The semiconductor device of claim 14, further comprising:
an outer protective layer covering the semiconductor substrate;
a barrier layer disposed between the outer protective layer and the semiconductor substrate;
wherein
the electrical pad and the thermal pad are attached over the outer protective layer and the semiconductor substrate; and
the extension extends at least partially through the outer protective layer.

### Claim 16 (depends on 15)

The semiconductor device of claim 15, wherein:
the outer protective layer includes a tetraethyl orthosilicate (TEOS) layer; and
the extension extends through the TEOS layer and up to the barrier layer.

### Claim 17 (depends on 14)

The semiconductor device of claim 14, further comprising:
a through silicon via (TSV) electrically coupled to the electrical pad and the active circuitry, the TSV having a TSV length that is greater than a length of the electrically-isolated extension.

### Claim 18 (depends on 14)

The semiconductor device of claim 14, the extension is one vertical extension within a set of vertical extensions, vertical extensions in the set of vertical extensions being:
directly attached to the thermal pad,
separated from each other by at least a lateral separation distance,
arranged within an area under the thermal pad and having a width less than a width of the connection pad, and
electrically isolated from the active circuitry and the semiconductor circuitry.

### Claim 19

A method of manufacturing a semiconductor device, the method comprising:
providing a semiconductor substrate having active circuitry on a frontside of the semiconductor substrate;
forming a protective outer layer over a backside of the semiconductor substrate;
forming a depression extending at least partially through the protective outer layer and toward the semiconductor substrate;
forming an electrically-isolated extension in the depression, wherein the electrically-isolated extension is electrically isolated from the active circuitry; and
attaching a connection pad over the protective outer layer and coupled to the electrically-isolated extension.

### Claim 20 (depends on 19)

The method of claim 19, further comprising:
forming a barrier layer over the semiconductor substrate and a through-silicon via (TSV) before forming the protective outer layer;
removing a portion of the barrier layer, a portion of the protective outer layer, a portion of the electrically-isolated extension, or a combination thereof to expose the TSV;
attaching an electrical pad attached to the TSV;
wherein:
the connection pad is a thermal pad configured to provide an external thermal interface for removing thermal energy from the semiconductor device;
the electrically-isolated extension includes a thermally conductive material and is thermally coupled to the thermal pad; and
the protective outer layer is formed over the barrier layer and covers the TSV.