# US 2023/0056494 A1 · Semiconductor memory device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2023/0056494 A1 - Document ID: US20230056494A1 - Status: Published application - Kind: A1 - Application number: 17/695,529 - Filed: 2022-03-15 - Published: 2023-02-23 - Earliest claimed: 2021-08-18 - Assignees: Kioxia Corporation - Applicants: Kioxia Corporation - Inventors: Wataru MORIYAMA; Hayato KONNO; Takao NAKAJIMA; Fumihiro KONO; Masaki FUJIU; Kiyoaki IWASA; Tadashi SOMEYA - Web page: https://patentgrep.com/patent/US20230056494A1 ## CPC - G11C 16/16: for erasing blocks, e.g. arrays, words, groups - G11C 16/0483: {comprising cells having several storage transistors connected in series} - G11C 16/08: Address circuits; Decoders; Word-line control circuits - G11C 16/24: Bit-line control circuits - G11C 16/32: Timing circuits - H10B 41/27: the channels comprising vertical portions, e.g. U-shaped channels - H10B 43/27: the channels comprising vertical portions, e.g. U-shaped channels - H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV] - H10W 20/43: Layouts of interconnections - G11C: STATIC STORES (semiconductor memory devices H10B) - H10B: ELECTRONIC MEMORY DEVICES - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract A semiconductor memory device includes a plurality of word lines, a first select gate line, a second select gate line, a first semiconductor layer, a third select gate line, a fourth select gate line, a second semiconductor layer, and a word line contact electrode. The first select gate line and the third select gate line are farther from the substrate than the plurality of word lines. The second select gate line and the fourth select gate line are closer to the substrate than the plurality of word lines. The first semiconductor layer is opposed to the plurality of word lines, the first select gate line, and the second select gate line. The second semiconductor layer is opposed to the plurality of word lines, the third select gate line, and the fourth select gate line. The word line contact electrode is connected to one of the plurality of word lines. ## Claims ### Claim 1 A semiconductor memory device comprising: a substrate that includes a first region and a second region arranged in a first direction and a third region disposed between the first region and the second region; a plurality of word lines extending in the first direction across the first region, the second region, and the third region, the plurality of word lines being arranged in a second direction intersecting with the first direction; a first select gate line that is disposed in the first region and farther from the substrate than the plurality of word lines; a second select gate line that is disposed in the first region and closer to the substrate than the plurality of word lines; a first semiconductor layer disposed in the first region, the first semiconductor layer extending in the second direction and being opposed to the plurality of word lines, the first select gate line, and the second select gate line; a first bit line extending in a third direction intersecting with the first direction and the second direction, the first bit line being disposed at a position overlapping with the first semiconductor layer viewed in the second direction; a third select gate line that is disposed in the second region and farther from the substrate than the plurality of word lines; a fourth select gate line that is disposed in the second region and closer to the substrate than the plurality of word lines; a second semiconductor layer disposed in the second region, the second semiconductor layer extending in the second direction and being opposed to the plurality of word lines, the third select gate line, and the fourth select gate line; a second bit line extending in the third direction, the second bit line being disposed at a position overlapping with the second semiconductor layer viewed in the second direction; and a word line contact electrode disposed in the third region, the word line contact electrode extending in the second direction and being connected to one of the plurality of word lines. ### Claim 2 (depends on 1) The semiconductor memory device according to claim 1, further comprising: a first transistor electrically connected to the first select gate line; a second transistor electrically connected to the second select gate line; a third transistor electrically connected to the third select gate line; and a fourth transistor electrically connected to the fourth select gate line. ### Claim 3 (depends on 1) The semiconductor memory device according to claim 1, further comprising: a first contact electrode disposed in the third region, the first contact electrode extending in the second direction and being connected to the first select gate line; a second contact electrode disposed in the third region, the second contact electrode extending in the second direction and being connected to the second select gate line; a third contact electrode disposed in the third region, the third contact electrode extending in the second direction and being connected to the third select gate line; and a fourth contact electrode disposed in the third region, the fourth contact electrode extending in the second direction and being connected to the fourth select gate line. ### Claim 4 (depends on 1) The semiconductor memory device according to claim 1, further comprising a source line connected to the first semiconductor layer and the second semiconductor layer. ### Claim 5 (depends on 1) The semiconductor memory device according to claim 1, further comprising a control circuit configured to perform a first erase operation by: applying a first voltage to the first select gate line; applying a second voltage to the second select gate line; applying a third voltage to the third select gate line; and applying a fourth voltage to the fourth select gate line, wherein the first voltage is smaller than the third voltage, and the second voltage is smaller than the fourth voltage. ### Claim 6 (depends on 5) The semiconductor memory device according to claim 5, further comprising a source line connected to the first semiconductor layer and the second semiconductor layer, wherein the control circuit configured to perform the first erase operation by: applying a first erase voltage larger than the first voltage and the second voltage to the first bit line; and applying a second erase voltage larger than the first voltage and the second voltage to the source line. ### Claim 7 (depends on 1) The semiconductor memory device according to claim 1, further comprising: a first source line connected to the first semiconductor layer; and a second source line connected to the second semiconductor layer. ### Claim 8 (depends on 1) The semiconductor memory device according to claim 1, further comprising a control circuit configured to perform a first erase operation by: applying a first voltage to the first select gate line; applying a second voltage to the second select gate line; applying a third voltage to the third select gate line; and applying a fourth voltage to the fourth select gate line, wherein the first voltage is larger than the third voltage, and the second voltage is larger than the fourth voltage. ### Claim 9 (depends on 8) The semiconductor memory device according to claim 8, further comprising: a first source line connected to the first semiconductor layer; and a second source line connected to the second semiconductor layer, wherein the control circuit configured to perform the first erase operation by: applying a first erase voltage larger than the first voltage and the second voltage to the first bit line; applying a fifth voltage smaller than the first erase voltage to the second bit line; applying a second erase voltage larger than the first voltage and the second voltage to the first source line; and applying a sixth voltage smaller than the second erase voltage to the second source line. ### Claim 10 (depends on 1) The semiconductor memory device according to claim 1, wherein the substrate includes: a fourth region farther from the third region than the first region; and a fifth region farther from the third region than the second region, and the semiconductor memory device includes: a fifth select gate line that is disposed in the fourth region and farther from the substrate than the plurality of word lines; a sixth select gate line that is disposed in the fourth region and closer to the substrate than the plurality of word lines; a third semiconductor layer disposed in the fourth region, the third semiconductor layer extending in the second direction and being opposed to the plurality of word lines, the fifth select gate line, and the sixth select gate line; a third bit line extending in the third direction, the third bit line being disposed at a position overlapping with the third semiconductor layer viewed in the second direction; a seventh select gate line that is disposed in the fifth region and farther from the substrate than the plurality of word lines; an eighth select gate line that is disposed in the fifth region and closer to the substrate than the plurality of word lines; a fourth semiconductor layer disposed in the fifth region, the fourth semiconductor layer extending in the second direction and being opposed to the plurality of word lines, the seventh select gate line, and the eighth select gate line; and a fourth bit line extending in the third direction, the fourth bit line being disposed at a position overlapping with the fourth semiconductor layer viewed in the second direction. ### Claim 11 (depends on 10) The semiconductor memory device according to claim 10, further comprising: a fifth transistor electrically connected to the fifth select gate line; a sixth transistor electrically connected to the sixth select gate line; a seventh transistor electrically connected to the seventh select gate line; and an eighth transistor electrically connected to the eighth select gate line. ### Claim 12 (depends on 10) The semiconductor memory device according to claim 10, wherein the substrate includes: a sixth region farther from the third region than the fourth region; and a seventh region farther from the third region than the fifth region, and the semiconductor memory device comprises: a fifth contact electrode disposed in the sixth region, the fifth contact electrode extending in the second direction and being connected to the fifth select gate line; a sixth contact electrode disposed in the sixth region, the sixth contact electrode extending in the second direction and being connected to the sixth select gate line; a seventh contact electrode disposed in the seventh region, the seventh contact electrode extending in the second direction and being connected to the seventh select gate line; and an eighth contact electrode disposed in the seventh region, the eighth contact electrode extending in the second direction and being connected to the eighth select gate line. ### Claim 13 (depends on 10) The semiconductor memory device according to claim 10, further comprising a source line connected to the third semiconductor layer and the fourth semiconductor layer. ### Claim 14 (depends on 10) The semiconductor memory device according to claim 10, further comprising: a first source line connected to the first semiconductor layer; a second source line connected to the second semiconductor layer; a third source line connected to the third semiconductor layer; and a fourth source line connected to the fourth semiconductor layer. ### Claim 15 (depends on 1) The semiconductor memory device according to claim 1, further comprising: a plurality of first memory cells disposed between the first select gate line and the second select gate line; a plurality of second memory cells disposed between the third select gate line and the fourth select gate line; and a control circuit configured to perform a first erase operation corresponding to an input of a first command set, wherein the first command set includes information to designate any one of the plurality of first memory cells or the plurality of second memory cells. ### Claim 16 (depends on 15) The semiconductor memory device according to claim 15, further comprising: a first memory block that includes the plurality of first memory cells; and a second memory block that includes the plurality of second memory cells. ### Claim 17 (depends on 10) The semiconductor memory device according to claim 10, further comprising: a plurality of first memory cells disposed between the first select gate line and the second select gate line; a plurality of second memory cells disposed between the third select gate line and the fourth select gate line; a plurality of third memory cells disposed between the fifth select gate line and the sixth select gate line; a plurality of fourth memory cells disposed between the seventh select gate line and the eighth select gate line; and a control circuit configured to perform a first erase operation corresponding to an input of a first command set, wherein the first command set includes information to designate any of the plurality of first memory cells, the plurality of second memory cells, the plurality of third memory cells, or the plurality of fourth memory cells. ### Claim 18 (depends on 17) The semiconductor memory device according to claim 17, further comprising: a first memory block that includes the plurality of first memory cells; a second memory block that includes the plurality of second memory cells; a third memory block that includes the plurality of third memory cells; and a fourth memory block that includes the plurality of fourth memory cells.