# US 2023/0056476 A1 · Low-latency forward error correction for high-speed serial links > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2023/0056476 A1 - Document ID: US20230056476A1 - Status: Published application - Kind: A1 - Application number: 17/978,832 - Filed: 2022-11-01 - Published: 2023-02-23 - Earliest claimed: 2019-02-15 - Assignees: Intel Corporation - Applicants: Intel Corporation - Inventors: Debendra Das Sharma - Web page: https://patentgrep.com/patent/US20230056476A1 ## CPC - H04L 1/0041: {Arrangements at the transmitter end} - H04L 1/0063: {Single parity check} - H04L 1/0045: {Arrangements at the receiver end} - H04L 1/0057: {Block codes (H04L1/0061, H04L1/0064 take precedence)} - H04L 1/0061: {Error detection codes} - H04L 1/0071: {Use of interleaving (interleaving per se H03M13/27)} - H04L 1/1692: {Physical properties of the supervisory signal, e.g. acknowledgement by energy bursts} - H04L: TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION (arrangements common to telegraphic and telephonic communication H04M) ## Abstract Systems and devices can include a port for transmitting data; and a link coupled to the port. The port, in preparation to transmit a data block across the link, to determine a size of a burst of data to be transmitted across the link; determine a plurality of error correcting code words for forward error correction based on the size of the burst of data; interleave each of the plurality of error correcting code words to correspond with consecutive symbols of the burst of data; and transmit the burst of data comprising the interleaved plurality of error correcting code across the link. ## Claims ### Claim 1 An apparatus comprising: a port for transmitting data across a link, the link comprising multiple lanes; and a link coupled to the port, the port to: determine a data block to be transmitted across the link; determine a plurality of error correcting code symbols for forward error correction; interleave each of the plurality of error correcting code symbols across each lane of the multilane link to correspond with consecutive symbols of the data block; and transmit the data block comprising the interleaved plurality of error correcting code across the link. ### Claim 2 (depends on 1) The apparatus of claim 1, wherein the port is to: determine a plurality of error correcting code based on a size of the data block by determining a number of consecutive symbols the data block will utilize; and identify a number of error correcting code symbols for each of the consecutive symbols of the data block. ### Claim 3 (depends on 1) The apparatus of claim 1, wherein the port is to: divide a data block into a subset of symbols; determine a number of consecutive symbols forming the subset of symbols that spans the entire number of bits forming data block; and determine a number of error correcting code symbols based on the number of consecutive symbols. ### Claim 4 (depends on 3) The apparatus of claim 3, wherein an error correcting code word from the plurality of error correcting code symbols corresponds to one symbol from the number of consecutive symbols. ### Claim 5 (depends on 1) The apparatus of claim 1, wherein three consecutive bytes in a data block comprise three different error correcting code symbols. ### Claim 6 (depends on 1) The apparatus of claim 1, wherein error correcting code symbols are defined over GF(28). ### Claim 7 (depends on 1) The apparatus of claim 1, wherein error correcting code symbols are defined based on: α being the root of any primitive polynomial of degree b, the powers of α represent the elements of GF(2b), which are distinct for powers of 0 through 2b−2. ### Claim 8 (depends on 1) The apparatus of claim 1, wherein error correcting code symbols are defined based on an H matrix comprising horizontal parity and check bits. ### Claim 9 A method comprising: determining a plurality of error correcting code symbols for forward error correction based on the size of the data block; interleaving each of the plurality of error correcting code symbols across each lane of the multilane link to correspond with consecutive symbols of the data block; and transmitting the data block comprising the interleaved plurality of error correcting code across the link. ### Claim 10 (depends on 9) The method of claim 9, further comprising: determining a plurality of error correcting code symbols based on a size of the data block by determining a number of consecutive symbols the data block will utilize; and identifying a number of error correcting code symbols for each of the consecutive symbols of the data block. ### Claim 11 (depends on 9) The method of claim 9, further comprising: dividing a data block into a subset of symbols; determining a number of consecutive symbols forming the subset of symbols that spans the entire number of bits forming data block; and determining a number of error correcting code symbols based on the number of consecutive symbols. ### Claim 12 (depends on 11) The method of claim 11, wherein an error correcting code word from the plurality of error correcting code symbols corresponds to one symbol from the number of consecutive symbols. ### Claim 13 (depends on 9) The method of claim 9, wherein three consecutive bytes in a data block comprise three different error correcting code symbols. ### Claim 14 (depends on 9) The method of claim 9, wherein error correcting code symbols are defined over GF(28). ### Claim 15 (depends on 9) The method of claim 9, wherein error correcting code symbols are defined based on: α being the root of any primitive polynomial of degree b, the powers of α represent the elements of GF(2b), which are distinct for powers of 0 through 2b−2. ### Claim 16 (depends on 9) The method of claim 9, wherein error correcting code symbols are defined based on an H matrix comprising horizontal parity and check bits. ### Claim 17 An apparatus comprising: a port to receive data; and a link comprising multiple lanes coupled to the port, the port comprising hardware circuitry to: receive a data block from across the link; calculate row parity and check bits for the received data block using a parity-check matrix; compare the calculated row parity and check bits against row parity and check bits received in the data block, the data block comprising multiple error correcting code words interleaved among consecutive symbols of the data block; and correct errors based on the comparison of the calculated row parity and check bits against the received row parity and check bits received in the data block. ### Claim 18 (depends on 17) The apparatus of claim 17, the port to decode the multiple error correcting code words using a parity-check matrix. ### Claim 19 (depends on 17) The apparatus of claim 17, the port to decode multiple error correcting code words from a received data block, each of the multiple error correcting code words overlapping one or more consecutive sets of symbols, wherein each symbol comprises a plurality of consecutive bits.