# US 2023/0056423 A1 · Processor core simulator including trace-based coherent cache driven memory traffic generator > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2023/0056423 A1 - Document ID: US20230056423A1 - Status: Published application - Kind: A1 - Application number: 17/405,420 - Filed: 2021-08-18 - Published: 2023-02-23 - Earliest claimed: 2021-08-18 - Assignees: International Business Machines Corporation - Applicants: International Business Machines Corporation - Inventors: Mohit Karve - Web page: https://patentgrep.com/patent/US20230056423A1 ## CPC - G06F 30/20: Design optimisation, verification or simulation (optimisation, verification or simulation of circuit designs G06F30/30) - G06F 30/3308: using simulation - G06F 12/0811: with multilevel cache hierarchies - G06F 12/0862: with prefetch - G06F 12/0895: of parts of caches, e.g. directory or tag array - G06F 2115/10: Processors - G06F 2212/1008: Correctness of operation, e.g. memory ordering - G06F 2212/1016: Performance improvement - G06F 2212/1021: Hit rate improvement - G06F 2212/602: Details relating to cache prefetching - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract A core simulator includes one or more simulated processors, a trace-based traffic generator, and a simulated memory subsystem. Each simulated processor includes a core element and at least one lower-level cache excluded from the core element. The trace-based traffic generator includes a plurality of modeled caches that model the at least lower-level cache without modeling the core element. The trace-based traffic generator is configured to receive at least one workload trace and based on the workload trace simulate actual memory traffic to be processed by the simulated memory subsystem. The simulated memory subsystem is shared between the at least one simulated processor and the trace-based traffic generator. The trace-based traffic generator performs a data exchange with the memory subsystem based on the at least one workload trace. The data exchange impacts a measured performance of the at least one simulated processor. ## Claims ### Claim 1 A computer system comprising a core simulator, the core simulator comprising: at least one simulated processor including a core element and at least one lower-level cache excluded from the core element; a trace-based traffic generator that includes a plurality of modeled caches that model the at least one lower-level cache without modeling the core element, the trace-based traffic generator configured to receive at least one workload trace and based on the workload trace simulate actual memory traffic to be processed by the at least one simulated processor; and a memory subsystem that is shared between the at least one simulated processor and the trace-based traffic generator, wherein the trace-based traffic generator performs a data exchange with the memory subsystem based on the at least one workload trace, the data exchange impacting a measured performance of the at least one simulated processor. ### Claim 2 (depends on 1) The computer system of claim 1, wherein the at least one lower-level cache includes a first lower-level cache and a second lower-level cache having a lower hierarchy than the first lower-level cache. ### Claim 3 (depends on 2) The computer system of claim 2, wherein the first lower-level cache and a second lower-level cache are exclusive of one another. ### Claim 4 (depends on 3) The computer system of claim 3, wherein the first lower-level cache has a first cache size and the second lower-level cache has a second cache size, and wherein each modeled cache included in the plurality of modeled caches has an effective cache size defined as a sum of the first cache size and the second cache size. ### Claim 5 (depends on 3) The computer system of claim 3, wherein the data exchange includes at least one signal selected among the group comprising a cache line read signal, a returned cache line signal, and a reload signal. ### Claim 6 (depends on 5) The computer system of claim 5, wherein the trace-based traffic generator further comprises a plurality of prefetchers, each prefetcher associated with a respective modeled cache. ### Claim 7 (depends on 6) The computer system of claim 6, wherein the data exchange further includes a memory bandwidth utilization signal indicating a current memory usage of the memory subsystem, and wherein a given prefetch among the plurality of prefetchers dynamically determines an amount of data to prefetch based on the memory bandwidth utilization signal. ### Claim 8 A computer implemented method comprising: simulating at least one processor including a core element and at least one lower-level cache excluded from the core element; simulating a trace-based traffic generator that includes a plurality of modeled caches that model the at least one lower-level cache without modeling the core element, the simulated trace-based traffic generator configured to receive at least one workload trace and based on the workload trace simulate actual memory traffic; and simulating a memory subsystem that is shared between the at least one simulated processor and the simulated trace-based traffic generator, wherein the simulated trace-based traffic generator performs a data exchange with the simulated memory subsystem based on the at least one workload trace, the data exchange impacting a measured performance of the at least one simulated processor. ### Claim 9 (depends on 8) The method of claim 8, wherein the at least one lower-level cache includes a first lower-level cache and a second lower-level cache having a lower hierarchy than the first lower-level cache. ### Claim 10 (depends on 9) The method of claim 9, wherein the first lower-level cache and a second lower-level cache are exclusive of one another. ### Claim 11 (depends on 10) The method of claim 10, wherein the first lower-level cache has a first cache size and the second lower-level cache has a second cache size, and wherein each modeled cache included in the plurality of modeled caches has an effective cache size defined as a sum of the first cache size and the second cache size. ### Claim 12 (depends on 10) The method of claim 10, wherein the data exchange includes at least one signal selected among the group comprising a cache line read signal, a returned cache line signal, and a reload signal. ### Claim 13 (depends on 12) The method of claim 12, wherein the simulated trace-based traffic generator further comprises a plurality of prefetchers, each prefetcher associated with a respective modeled cache. ### Claim 14 (depends on 13) The method of claim 13, wherein the data exchange further includes a memory bandwidth utilization signal indicating a current memory usage of the memory subsystem, and wherein a given prefetch among the plurality of prefetchers dynamically determines an amount of data to prefetch based on the memory bandwidth utilization signal. ### Claim 15 A computer program product comprising a computer readable storage medium having program instructions embodied therewith, the program instructions executable by one or more processors to cause the one or more processors to perform operations comprising: simulating at least one processor including a core element and at least one lower-level cache excluded from the core element; simulating a trace-based traffic generator that includes a plurality of modeled caches that model the at least one lower-level cache without modeling the core element, the simulated trace-based traffic generator configured to receive at least one workload trace and based on the workload trace simulate actual memory traffic; and simulating a memory subsystem that is shared between the at least one simulated processor and the simulated trace-based traffic generator, wherein the simulated trace-based traffic generator performs a data exchange with the simulated memory subsystem based on the at least one workload trace, the data exchange impacting a measured performance of the at least one simulated processor. ### Claim 16 (depends on 15) The computer program product of claim 15, wherein the at least one lower-level cache includes a first lower-level cache and a second lower-level cache having a lower hierarchy than the first lower-level cache. ### Claim 17 (depends on 16) The computer program product of claim 16, wherein the first lower-level cache and a second lower-level cache are exclusive of one another. ### Claim 18 (depends on 17) The computer program product of claim 17, wherein the first lower-level cache has a first cache size and the second lower-level cache has a second cache size, and wherein each modeled cache included in the plurality of modeled caches has an effective cache size defined as a sum of the first cache size and the second cache size. ### Claim 19 (depends on 17) The computer program product of claim 17, wherein the data exchange includes at least one signal selected among the group comprising a cache line read signal, a returned cache line signal, and a reload signal. ### Claim 20 (depends on 19) The computer program product of claim 19, wherein the simulated trace-based traffic generator further comprises a plurality of prefetchers, each prefetcher associated with a respective modeled cache, wherein the data exchange further includes a memory bandwidth utilization signal indicating a current memory usage of the memory subsystem, and wherein a given prefetch among the plurality of prefetchers dynamically determines an amount of data to prefetch based on the memory bandwidth utilization signal.