# US 2023/0056041 A1 · Semiconductor package and method of manufacturing the same

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- Number: US 2023/0056041 A1
- Document ID: US20230056041A1
- Status: Published application
- Kind: A1
- Application number: 17/706,978
- Filed: 2022-03-29
- Published: 2023-02-23
- Earliest claimed: 2021-08-20
- Assignees: Samsung Electronics Co., Ltd.
- Applicants: Samsung Electronics Co., Ltd.
- Inventors: Dongkyu Kim; Jongyoun Kim; Seokhyun Lee; Minjung Kim
- Web page: https://patentgrep.com/patent/US20230056041A1

## CPC

- H10W 90/00: Package configurations
- H10W 70/611: {for connecting multiple chips together}
- H10W 70/685: comprising multiple insulating layers
- H10W 74/131: {the semiconductor body being only partially enclosed}
- H10W 90/401: {characterised by multiple insulating or insulated package substrates, interposers or RDLs}
- H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts}
- H10W 72/823: {Interconnections through encapsulations, e.g. pillars through molded resin on a lateral side a chip}
- H10W 74/014: {using batch processing}
- H10W 74/117: {the substrate having spherical bumps for external connection}
- H10W 90/20: Configurations of stacked chips
- H10W 90/28: the stacked chips having different sizes, e.g. chip stacks having a pyramidal shape
- H10W 90/291: {characterised by containers, encapsulations, or other housings for the stacked chips}
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor package includes: a base substrate including a lower redistribution layer; a lower semiconductor chip including a first active surface and on the base substrate; an upper semiconductor chip including a second active surface on the lower semiconductor chip and having an area larger than that of the lower semiconductor chip; an intermediate connection member including an upper redistribution layer on the second active surface of the upper semiconductor chip between the lower and upper semiconductor chips; a plurality of vertical interconnectors disposed around the lower semiconductor chip on the base substrate and connecting the lower redistribution layer and the upper redistribution layer; and a molding portion on the base substrate and including a first portion surrounding the lower semiconductor chip and the vertical interconnectors, and a second portion extending upwardly from the first portion and on side surfaces of the upper semiconductor chip and the intermediate connection member.

## Claims

### Claim 1

A semiconductor package comprising:
a base substrate including a lower redistribution layer;
a lower semiconductor chip including a first active surface with first connection pads thereon, the lower semiconductor chip on the base substrate such that the first active surface faces an upper surface of the base substrate, each of the first connection pads being connected to the lower redistribution layer;
an upper semiconductor chip including a second active surface with second connection pads thereon, the upper semiconductor chip on the lower semiconductor chip such that the second active surface faces the lower semiconductor chip, the upper semiconductor chip having an area larger than an area of the lower semiconductor chip;
an intermediate connection member including an upper redistribution layer on the second active surface of the upper semiconductor chip between the lower semiconductor chip and the upper semiconductor chip and connected to the second connection pads;
a plurality of vertical interconnectors disposed around the lower semiconductor chip on the base substrate and connecting the lower redistribution layer and the upper redistribution layer; and
a molding portion on the base substrate and including a first portion surrounding the lower semiconductor chip and the plurality of vertical interconnectors, and a second portion extending from the first portion and on side surfaces of the upper semiconductor chip and the intermediate connection member.

### Claim 2 (depends on 1)

The semiconductor package of claim 1, wherein:
the second portion of the molding portion has a thickness ranging from 10 μm to 300 μm.

### Claim 3 (depends on 1)

The semiconductor package of claim 1, wherein:
the second portion of the molding portion surrounds an entirety of the side surfaces of the upper semiconductor chip and the intermediate connection member.

### Claim 4 (depends on 1)

The semiconductor package of claim 1, wherein:
the upper semiconductor chip includes a second inactive surface opposite the second active surface; and
the second inactive surface of the upper semiconductor chip is substantially coplanar with an upper surface of the second portion of the molding portion.

### Claim 5 (depends on 1)

The semiconductor package of claim 1, wherein:
the intermediate connection member has an area corresponding to that of the second active surface of the upper semiconductor chip.

### Claim 6 (depends on 1)

The semiconductor package of claim 1, wherein:
the base substrate has an area larger than an area of the intermediate connection member.

### Claim 7 (depends on 6)

The semiconductor package of claim 6, wherein:
the base substrate includes a side surface that is substantially coplanar with a side surface of the molding portion.

### Claim 8 (depends on 1)

The semiconductor package of claim 1, wherein:
the lower semiconductor chip includes a plurality of semiconductor chips.

### Claim 9 (depends on 1)

The semiconductor package of claim 1, wherein:
the upper redistribution layer includes a plurality of redistribution patterns and a plurality of vias connected to the plurality of redistribution patterns; and
the plurality of vias include vias that are directly connected to the second connection pads.

### Claim 10 (depends on 1)

The semiconductor package of claim 1, wherein:
the molding portion includes a third portion covering the first active surface of the lower semiconductor chip; and
the semiconductor package further comprises a plurality of conductive posts respectively disposed on the first connection pads and penetrating through the third portion of the molding portion, and the lower redistribution layer is connected to the plurality of conductive posts.

### Claim 11 (depends on 1)

The semiconductor package of claim 1, wherein:
the lower redistribution layer includes a plurality of redistribution patterns and a plurality of vias connected to the plurality of redistribution patterns; and
the plurality of vias include vias that are directly connected to the first connection pads.

### Claim 12 (depends on 1)

The semiconductor package of claim 1, wherein:
the lower semiconductor chip includes a first inactive surface opposite the first active surface; and
the semiconductor package further includes a bonding layer between the first inactive surface of the lower semiconductor chip and the intermediate connection member.

### Claim 13 (depends on 1)

The semiconductor package of claim 1, wherein:
the lower semiconductor chip includes a memory chip, and the upper semiconductor chip includes a processor chip.

### Claim 14

A semiconductor package comprising:
a base substrate including a lower redistribution layer;
a lower semiconductor chip including a first active surface with first connection pads thereon and a first inactive surface opposite the first active surface, the lower semiconductor chip on the base substrate such that the first active surface faces the base substrate, the first connection pads being connected to the lower redistribution layer;
an upper semiconductor chip having an area larger than an area of the lower semiconductor chip and including a second active surface with second connection pads thereon and a second inactive surface opposite the second active surface, the upper semiconductor chip on the lower semiconductor chip such that the second active surface faces the lower semiconductor chip;
an intermediate connection member including an upper redistribution layer on the second active surface of the upper semiconductor chip between the lower semiconductor chip and the upper semiconductor chip and connected to each of the second connection pads;
a plurality of vertical interconnectors disposed around the lower semiconductor chip on the base substrate and connecting the lower redistribution layer and the upper redistribution layer to each other; and
a molding layer on the base substrate surrounding the lower semiconductor chip and the plurality of vertical interconnectors and extending upwardly along side surfaces of the upper semiconductor chip and the intermediate connection member, the molding layer including an upper surface that is substantially coplanar with the second inactive surface of the upper semiconductor chip.

### Claim 15 (depends on 14)

The semiconductor package of claim 14, wherein:
the base substrate has an area larger than an area of the intermediate connection member; and
the base substrate includes a side surface that is substantially coplanar with a side surface of the molding layer.

### Claim 16 (depends on 14)

The semiconductor package of claim 14, wherein:
the molding layer includes a portion covering the first active surface of the lower semiconductor chip; and
the semiconductor package further includes conductive posts penetrating through the portion of the molding layer covering the first active surface to connect each of the first connection pads of the lower semiconductor chip to the lower redistribution layer.

### Claim 17

A semiconductor package comprising:
a first semiconductor chip including a first surface with first connection pads thereon and a second surface opposite the first surface;
a first connection member on the first surface of the first semiconductor chip and including a first redistribution layer electrically connected to the first connection pads, the first connection member having the same area as the first semiconductor chip;
a second semiconductor chip including a first surface with second connection pads thereon and a second surface opposite the first surface and bonded to one region of the first connection member;
a second connection member on the second surface of the second semiconductor chip and including a second redistribution layer electrically connected to the second connection pads, the second connection member having an area larger than an area of the first semiconductor chip;
a plurality of vertical interconnectors disposed around the second semiconductor chip on the second connection member and connecting the first redistribution layer and the second redistribution layer to each other; and
a molding portion on the second connection member surrounding the second semiconductor chip and the plurality of vertical interconnectors and extending upwardly on side surfaces of the first semiconductor chip and the first connection member.

### Claim 18 (depends on 17)

The semiconductor package of claim 17, wherein:
the first redistribution layer includes a plurality of first redistribution patterns and a plurality of vias connected to the plurality of first redistribution pattern, each of the plurality of vias having a width that decreases in a direction toward the first surface of the first semiconductor chip; and
the plurality of vias include vias connected to the first connection pads.

### Claim 19 (depends on 17)

The semiconductor package of claim 17, wherein:
the second redistribution layer includes a plurality of second redistribution patterns and a plurality of second vias connected to the plurality of second redistribution patterns, each of the plurality of second vias having a width that decreases in a direction toward the first surface of the second semiconductor chip; and
the plurality of second vias include vias connected to the second connection pads.

### Claim 20 (depends on 17)

The semiconductor package of claim 17, wherein:
the first surface of the first semiconductor chip is substantially coplanar with an upper surface of the molding portion.

### Claim at position 21

21-25. (canceled)