# US 2023/0055464 A1 · Drc test pattern generation method and apparatus, electronic device, and storage medium > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2023/0055464 A1 - Document ID: US20230055464A1 - Status: Published application - Kind: A1 - Application number: 17/658,516 - Filed: 2022-04-08 - Published: 2023-02-23 - Earliest claimed: 2021-08-13 - Assignees: Changxin Memory Technologies, Inc. - Applicants: Changxin Memory Technologies, Inc. - Inventors: Chuanjiang CHEN; Li BAI; Kang ZHAO - Web page: https://patentgrep.com/patent/US20230055464A1 ## CPC - G06F 30/398: Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] (optical proximity correction [OPC] design processes G03F1/36) - G06F 30/392: Floor-planning or layout, e.g. partitioning or placement - G06F 2111/02: CAD in a network environment, e.g. collaborative CAD or distributed simulation - G06F 2119/18: Manufacturability analysis or optimisation for manufacturability - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract A DRC test pattern generation method includes: receiving a DRC test pattern generation request, the DRC test pattern generation request carrying the number of correct patterns and the number of erroneous patterns; acquiring layout design rule information and corresponding layer configuration information, the layer configuration information including process layer configuration parameter information that is set according to a process type; parsing parameter information corresponding to each rule in the layout design rule information and the process layer configuration parameter information in the layer configuration information, and generating formatted parameter information corresponding to the each rule; and generating a corresponding number of correct patterns and a corresponding number of erroneous patterns corresponding to each rule according to the formatted parameter information. ## Claims ### Claim 1 A design rule check (DRC) test pattern generation method, comprising: receiving a DRC test pattern generation request, wherein the DRC test pattern generation request carries a number of correct patterns and a number of erroneous patterns; acquiring layout design rule information and corresponding layer configuration information, wherein the layer configuration information comprises process layer configuration parameter information that is set according to a process type; parsing parameter information corresponding to each rule in the layout design rule information and the process layer configuration parameter information in the layer configuration information, and generating formatted parameter information corresponding to the each rule according to the parameter information corresponding to the each rule, process layer configuration parameter information associated with the each rule, the number of correct patterns, and the number of erroneous patterns, respectively; and generating a corresponding number of correct patterns and a corresponding number of erroneous patterns corresponding to the each rule according to the formatted parameter information corresponding to the each rule. ### Claim 2 (depends on 1) The method of claim 1, wherein a formatted parameter comprises a rule parameter, a rule-related process layer configuration parameter, and a DRC test pattern generation step size parameter. ### Claim 3 (depends on 2) The method of claim 2, wherein the rule parameter at least comprises a rule type, a rule constraint interval, a type of a rule check trigger condition, and a layer constraint interval in the rule check trigger condition; the rule-related process layer configuration parameter comprises a layer of a rule check, a layer attribute parameter, and a layer in the rule check trigger condition; and the DRC test pattern generation step size parameter comprises a gradient value corresponding to the rule type and a gradient value corresponding to the type of the rule check trigger condition. ### Claim 4 (depends on 3) The method of claim 3, wherein the gradient value corresponding to the rule type is determined according to the rule constraint interval, the number of correct patterns, and the number of erroneous patterns; the gradient value corresponding to the type of the rule check trigger condition is determined according to the layer constraint interval in the rule check trigger condition, the number of correct patterns, and the number of erroneous patterns; wherein generating the corresponding number of correct patterns and the corresponding number of erroneous patterns corresponding to the each rule according to the formatted parameter information corresponding to the each rule specifically comprises: invoking a preset test pattern generation engine corresponding to the rule type of the each rule to generate, according to the gradient value corresponding to the rule type and the gradient value corresponding to the type of the rule check trigger condition, the corresponding number of correct patterns that satisfy the rule constraint interval and the corresponding number of erroneous patterns that do not satisfy the rule constraint interval corresponding to the each rule. ### Claim 5 (depends on 4) The method of claim 4, wherein the gradient value corresponding to the rule type is determined according to following modes: in response to determining that the rule constraint interval only comprises an interval lower limit value, determining a ratio of the interval lower limit value to the number of erroneous patterns as the gradient value corresponding to the rule type; and in response to determining that the rule constraint interval comprises an interval upper limit value, determining a ratio of the interval upper limit value to the number of correct patterns as the gradient value corresponding to the rule type. ### Claim 6 (depends on 4) The method of claim 4, wherein the gradient value corresponding to the type of the rule check trigger condition is determined according to following modes: in response to determining that the layer constraint interval in the rule check trigger condition only comprises an interval lower limit value, determining a ratio of the interval lower limit value to the number of erroneous patterns as the gradient value corresponding to the type of the rule check trigger condition; and in response to determining that the layer constraint interval in the rule check trigger condition comprises the interval lower limit value and an interval upper limit value, determining a ratio of a difference value between the interval upper limit value and the interval lower limit value to the number of erroneous patterns as the gradient value corresponding to the type of the rule check trigger condition. ### Claim 7 An electronic device, comprising a memory and a processor, wherein the memory is configured to store a computer program executable by the processor, wherein when executing the computer program, the processor is configured to: receive a DRC test pattern generation request, wherein the DRC test pattern generation request carries a number of correct patterns and a number of erroneous patterns; acquire layout design rule information and corresponding layer configuration information, wherein the layer configuration information comprises process layer configuration parameter information that is set according to a process type; parse parameter information corresponding to each rule in the layout design rule information and the process layer configuration parameter information in the layer configuration information, and generate formatted parameter information corresponding to the each rule according to the parameter information corresponding to the each rule, process layer configuration parameter information associated with the each rule, the number of correct patterns, and the number of erroneous patterns, respectively; and generate a corresponding number of correct patterns and a corresponding number of erroneous patterns corresponding to the each rule according to the formatted parameter information corresponding to the each rule. ### Claim 8 (depends on 7) The electronic device of claim 7, wherein a formatted parameter comprises a rule parameter, a rule-related process layer configuration parameter, and a DRC test pattern generation step size parameter. ### Claim 9 (depends on 8) The electronic device of claim 8, wherein the rule parameter at least comprises a rule type, a rule constraint interval, a type of a rule check trigger condition, and a layer constraint interval in the rule check trigger condition; the rule-related process layer configuration parameter comprises a layer of a rule check, a layer attribute parameter, and a layer in the rule check trigger condition; and the DRC test pattern generation step size parameter comprises a gradient value corresponding to the rule type and a gradient value corresponding to the type of the rule check trigger condition. ### Claim 10 (depends on 9) The electronic device of claim 9, wherein the gradient value corresponding to the rule type is determined according to the rule constraint interval, the number of correct patterns, and the number of erroneous patterns; the gradient value corresponding to the type of the rule check trigger condition is determined according to the layer constraint interval in the rule check trigger condition, the number of correct patterns, and the number of erroneous patterns; wherein the processor is specifically configured to: invoke a preset test pattern generation engine corresponding to the rule type of the each rule to generate, according to the gradient value corresponding to the rule type and the gradient value corresponding to the type of the rule check trigger condition, the corresponding number of correct patterns that satisfy the rule constraint interval and the corresponding number of erroneous patterns that do not satisfy the rule constraint interval corresponding to the each rule. ### Claim 11 (depends on 10) The electronic device of claim 10, wherein the gradient value corresponding to the rule type is determined according to following modes: in response to determining that the rule constraint interval only comprises an interval lower limit value, determining a ratio of the interval lower limit value to the number of erroneous patterns as the gradient value corresponding to the rule type; and in response to determining that the rule constraint interval comprises an interval upper limit value, determining a ratio of the interval upper limit value to the number of correct patterns as the gradient value corresponding to the rule type. ### Claim 12 (depends on 10) The electronic device of claim 10, wherein the gradient value corresponding to the type of the rule check trigger condition is determined according to following modes: in response to determining that the layer constraint interval in the rule check trigger condition only comprises an interval lower limit value, determining a ratio of the interval lower limit value to the number of erroneous patterns as the gradient value corresponding to the type of the rule check trigger condition; and in response to determining that the layer constraint interval in the rule check trigger condition comprises the interval lower limit value and an interval upper limit value, determining a ratio of a difference value between the interval upper limit value and the interval lower limit value to the number of erroneous patterns as the gradient value corresponding to the type of the rule check trigger condition. ### Claim 13 A nonvolatile computer-readable storage medium, having a computer program stored thereon, wherein when executed by a processor, the program is configured to: receive a DRC test pattern generation request, wherein the DRC test pattern generation request carries a number of correct patterns and a number of erroneous patterns; acquire layout design rule information and corresponding layer configuration information, wherein the layer configuration information comprises process layer configuration parameter information that is set according to a process type; parse parameter information corresponding to each rule in the layout design rule information and the process layer configuration parameter information in the layer configuration information, and generate formatted parameter information corresponding to the each rule according to the parameter information corresponding to the each rule, process layer configuration parameter information associated with the each rule, the number of correct patterns, and the number of erroneous patterns, respectively; and generate a corresponding number of correct patterns and a corresponding number of erroneous patterns corresponding to the each rule according to the formatted parameter information corresponding to the each rule. ### Claim 14 (depends on 13) The storage medium of claim 13, wherein a formatted parameter comprises a rule parameter, a rule-related process layer configuration parameter, and a DRC test pattern generation step size parameter. ### Claim 15 (depends on 14) The storage medium of claim 14, wherein the rule parameter at least comprises a rule type, a rule constraint interval, a type of a rule check trigger condition, and a layer constraint interval in the rule check trigger condition; the rule-related process layer configuration parameter comprises a layer of a rule check, a layer attribute parameter, and a layer in the rule check trigger condition; and the DRC test pattern generation step size parameter comprises a gradient value corresponding to the rule type and a gradient value corresponding to the type of the rule check trigger condition. ### Claim 16 (depends on 15) The storage medium of claim 15, wherein the gradient value corresponding to the rule type is determined according to the rule constraint interval, the number of correct patterns, and the number of erroneous patterns; the gradient value corresponding to the type of the rule check trigger condition is determined according to the layer constraint interval in the rule check trigger condition, the number of correct patterns, and the number of erroneous patterns; wherein the program is specifically configured to: invoke a preset test pattern generation engine corresponding to the rule type of the each rule to generate, according to the gradient value corresponding to the rule type and the gradient value corresponding to the type of the rule check trigger condition, the corresponding number of correct patterns that satisfy the rule constraint interval and the corresponding number of erroneous patterns that do not satisfy the rule constraint interval corresponding to the each rule. ### Claim 17 (depends on 16) The storage medium of claim 16, wherein the gradient value corresponding to the rule type is determined according to following modes: in response to determining that the rule constraint interval only comprises an interval lower limit value, determining a ratio of the interval lower limit value to the number of erroneous patterns as the gradient value corresponding to the rule type; and in response to determining that the rule constraint interval comprises an interval upper limit value, determining a ratio of the interval upper limit value to the number of correct patterns as the gradient value corresponding to the rule type. ### Claim 18 (depends on 17) The storage medium of claim 17, wherein the gradient value corresponding to the type of the rule check trigger condition is determined according to following modes: in response to determining that the layer constraint interval in the rule check trigger condition only comprises an interval lower limit value, determining a ratio of the interval lower limit value to the number of erroneous patterns as the gradient value corresponding to the type of the rule check trigger condition; and in response to determining that the layer constraint interval in the rule check trigger condition comprises the interval lower limit value and an interval upper limit value, determining a ratio of a difference value between the interval upper limit value and the interval lower limit value to the number of erroneous patterns as the gradient value corresponding to the type of the rule check trigger condition.