# US 2023/0055422 A1 · Memory Arrays Comprising Strings Of Memory Cells And Methods Used In Forming A Memory Array Comprising Strings Of Memory Cells

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 2023/0055422 A1
- Document ID: US20230055422A1
- Status: Published application
- Kind: A1
- Application number: 17/409,476
- Filed: 2021-08-23
- Published: 2023-02-23
- Earliest claimed: 2021-08-23
- Assignees: Micron Technology, Inc.
- Applicants: Micron Technology, Inc.
- Inventors: Jordan D. Greenlee; John D. Hopkins; M. Jared Barclay; Andrew Li; Aireus Christensen
- Web page: https://patentgrep.com/patent/US20230055422A1

## CPC

- G11C 16/0483: {comprising cells having several storage transistors connected in series}
- H10B 41/10: characterised by the top-view layout
- H10B 41/27: the channels comprising vertical portions, e.g. U-shaped channels
- H10B 41/35: with a cell select transistor, e.g. NAND
- H10B 43/10: characterised by the top-view layout
- H10B 43/27: the channels comprising vertical portions, e.g. U-shaped channels
- H10B 43/35: with cell select transistors, e.g. NAND
- G11C: STATIC STORES (semiconductor memory devices H10B)
- H10B: ELECTRONIC MEMORY DEVICES

## Abstract

A method used in forming a memory array comprising strings of memory cells comprises forming a conductor tier comprising conductor material on a substrate. Laterally-spaced memory-block regions are formed that individually comprise a vertical stack comprising alternating first tiers and second tiers are formed directly above the conductor tier. Material of the first tiers is sacrificial and of different composition from material of the first tiers. Channel-material strings extend through the first tiers and the second tiers. Conducting material in a lowest of the first tiers is formed that directly electrically couples together the channel material of individual of the channel-material strings and the conductor material of the conductor tier. A horizontally-elongated trench is formed between immediately-laterally-adjacent of the memory-block regions. The trenches extend downwardly into the conducting material. After forming the trenches, lateral-sidewall regions of the conducting material that are aside the individual trenches in the lowest first tier is doped with an impurity. The sacrificial material is etched from the first tiers through the trenches selectively relative to the doped lateral-sidewall regions of the conducting material. Other embodiments, including structure, are disclosed.

## Claims

### Claim 1

A method used in forming a memory array comprising strings of memory cells, comprising:
forming a conductor tier comprising conductor material on a substrate;
forming laterally-spaced memory-block regions individually comprising a vertical stack comprising alternating first tiers and second tiers directly above the conductor tier, material of the first tiers being sacrificial and of different composition from material of the first tiers, channel-material strings extending through the first tiers and the second tiers;
forming conducting material in a lowest of the first tiers that directly electrically couples together the channel material of individual of the channel-material strings and the conductor material of the conductor tier;
a horizontally-elongated trench between immediately-laterally-adjacent of the memory-block regions, the trenches extending downwardly into the conducting material;
after forming the trenches, doping lateral-sidewall regions of the conducting material that are aside the individual trenches in the lowest first tier with an impurity; and
etching the sacrificial material from the first tiers through the trenches selectively relative to the doped lateral-sidewall regions of the conducting material.

### Claim 2 (depends on 1)

The method of claim 1 wherein the conducting material comprises floors in the lowest first tier that are individually directly under the individual trenches, and further comprising doping the floors of the conducting material with the impurity to form impurity-doped floor regions.

### Claim 3 (depends on 2)

The method of claim 2 wherein said doping the lateral-sidewall regions and said doping the floors occur at the same time.

### Claim 4 (depends on 2)

The method of claim 2 wherein two immediately-adjacent of the doped lateral-sidewall regions and the impurity-doped floor region laterally therebetween collectively join to comprise a generally U-shape in a vertical cross-section in the lowest first tier.

### Claim 5 (depends on 4)

The method of claim 4 wherein the lowest first tier has a top, the U of the generally U-shape having a top that is below the top of the lowest first tier.

### Claim 6 (depends on 4)

The method of claim 4 wherein the lowest first tier has a top, the U of the generally U-shape having a top that is elevationally-coincident with the top of the lowest first tier.

### Claim 7 (depends on 1)

The method of claim 1 wherein the trenches extend downwardly through all of the conducting material to the conductor material of the conductor tier.

### Claim 8 (depends on 7)

The method of claim 7 wherein the trenches extend into the conductor material of the conductor tier.

### Claim 9 (depends on 8)

The method of claim 8 wherein the conductor material comprises conductively-doped semiconductive material directly above and directly against metal material, the trenches extending into the conductively-doped semiconductive material and not to the metal material.

### Claim 10 (depends on 1)

The method of claim 1 wherein total impurity concentration in the lateral-sidewall regions is 0.05 to 30.0 atomic percent.

### Claim 11 (depends on 10)

The method of claim 10 wherein total impurity concentration in the lateral-sidewall regions is 0.5 to 10.0 atomic percent.

### Claim 12 (depends on 1)

The method of claim 1 wherein the impurity is at least one of B, C, N, Ga, and metal material.

### Claim 13 (depends on 12)

The method of claim 12 wherein total impurity concentration in the lateral-sidewall regions is 0.05 to 30.0 atomic percent.

### Claim 14 (depends on 12)

The method of claim 12 wherein the conducting material comprises conductively-phosphorus-doped silicon.

### Claim 15 (depends on 1)

The method of claim 1 wherein the doping comprises gas phase diffusion.

### Claim 16 (depends on 1)

The method of claim 1 wherein the doping comprises plasma enhanced doping.

### Claim 17 (depends on 1)

The method of claim 1 wherein the doping comprises ion implantation followed by anneal.

### Claim 18 (depends on 1)

The method of claim 1 wherein the conducting material comprises conductively-phosphorus-doped silicon and the impurity comprises B.

### Claim 19

A method used in forming a memory array comprising strings of memory cells, comprising:
forming a conductor tier comprising conductor material on a substrate;
forming a lower portion of a stack that will comprise vertically-alternating first tiers and second tiers above the conductor tier, the stack comprising laterally-spaced memory-block regions, a lowest of the first tiers comprising first sacrificial material;
forming the vertically-alternating first tiers and second tiers of an upper portion of the stack above the lower portion, and forming channel-material strings that extend through the upper portion to the lower portion, material of the first tiers in the upper portion comprising second sacrificial material that is of different composition from material of the first tiers;
forming horizontally-elongated trenches into the stack that are individually laterally-between immediately-laterally-adjacent of the memory-block regions, the trenches extending through the upper portion to the lowest first tier and exposing the first sacrificial material therein;
isotropically etching the exposed first sacrificial material from the lowest first tier through the trenches;
after the isotropically etching, forming conducting material in the lowest first tier that directly electrically couples together the channel material of the channel-material strings and the conductor material of the conductor tier;
after forming the trenches, doping lateral-sidewall regions of the conducting material that are aside the individual trenches in the lowest first tier with an impurity; and
etching the second sacrificial material from the first tiers in the upper portion through the trenches selectively relative to the doped lateral-sidewall regions of the conducting material in the lower portion.

### Claim 20 (depends on 19)

The method of claim 19 wherein the conducting material comprises floors in the lowest first tier that are individually directly under the individual trenches, and further comprising doping the floors of the conducting material with the impurity to form impurity-doped floor regions.

### Claim 21 (depends on 20)

The method of claim 20 wherein two immediately-adjacent of the doped lateral-sidewall regions and the impurity-doped floor region laterally therebetween collectively join to comprise a generally U-shape in a vertical cross-section in the lowest first tier.

### Claim 22 (depends on 19)

The method of claim 19 wherein the trenches extend downwardly through all of the conducting material to the conductor material of the conductor tier.

### Claim 23 (depends on 19)

The method of claim 19 wherein total impurity concentration in the lateral-sidewall regions is 0.05 to 30.0 atomic percent.

### Claim 24 (depends on 19)

The method of claim 19 wherein the impurity is at least one of B, C, N, Ga, and metal material.

### Claim 25 (depends on 19)

The method of claim 19 wherein the conducting material comprises conductively-phosphorus-doped silicon and the impurity comprises B.

### Claim 26

A memory array comprising strings of memory cells, comprising:
laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers above a conductor tier, strings of memory cells comprising channel-material strings that extend through the insulative tiers and the conductive tiers, conducting material in a lowest of the conductive tiers that directly electrically couples together the channel-material strings to conductor material of the conductor tier;
intervening material laterally-between, vertically-along, and longitudinally-along immediately-laterally-adjacent of the memory blocks; and
intermediate regions in the lowest first tier that are individually laterally between the intervening material and the conducting material, the intermediate regions comprising the conducting material having an impurity therein.

### Claim at position 27

27-37 (canceled)