# US 2023/0055293 A1 · Post error correction code registers for cache metadata > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2023/0055293 A1 - Document ID: US20230055293A1 - Status: Published application - Kind: A1 - Application number: 17/648,404 - Filed: 2022-01-19 - Published: 2023-02-23 - Earliest claimed: 2021-08-17 - Assignees: Micron Technology, Inc. - Applicants: Micron Technology, Inc. - Inventors: Taeksang Song; Saira Samar Malik; Chinnakrishnan Ballapuram - Web page: https://patentgrep.com/patent/US20230055293A1 ## CPC - G06F 11/1064: {in cache or content addressable memories} - G06F 9/30101: {Special purpose registers} - G06F 11/1048: {using arrangements adapted for a specific error detection or correction feature} - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract Methods, systems, and devices for post error correction code (ECC) registers for cache metadata are described. A device may read metadata from a memory array included in the device. The metadata may include information for operating a volatile memory as a cache for a non-volatile memory. The device may perform an ECC operation on the metadata based on reading the metadata from the memory array. After performing the ECC operation on the metadata, the device may write the metadata to a register that is coupled with the memory array. The device may then write the metadata from the register to the memory array. ## Claims ### Claim 1 An apparatus, comprising: a non-volatile memory; a volatile memory; and an interface controller coupled with the non-volatile memory and the volatile memory, the interface controller operable to cause the apparatus to: read metadata from a memory array included in the interface controller, the metadata comprising information for operating the volatile memory as a cache for the non-volatile memory; perform an error correction code (ECC) operation on the metadata based at least in part on reading the metadata from the memory array; write, based at least in part on performing the ECC operation, the metadata to a register that is coupled with the memory array; and write the metadata from the register to the memory array. ### Claim 2 (depends on 1) The apparatus of claim 1, wherein the interface controller is operable to cause the apparatus to: receive an activate command for a row of a bank in the volatile memory, wherein the metadata is read from the memory array based at least in part on the activate command. ### Claim 3 (depends on 2) The apparatus of claim 2, wherein the interface controller is operable to cause the apparatus to: receive a precharge command for the row of the bank in the volatile memory, wherein the metadata is written to the memory array based at least in part on the precharge command. ### Claim 4 (depends on 2) The apparatus of claim 2, wherein the interface controller is operable to cause the apparatus to: receive a read command or a write command for the row after receiving the activate command; and update the metadata in the register based at least in part on the read command or the write command. ### Claim 5 (depends on 2) The apparatus of claim 2, wherein the interface controller is operable to cause the apparatus to: determine the bank, of the memory array, that is associated with the metadata based at least in part on the activate command, wherein the metadata is written to the register based at least in part on the register being configured for the bank. ### Claim 6 (depends on 1) The apparatus of claim 1, wherein the interface controller is operable to cause the apparatus to: read parity bits for the metadata from the memory array, wherein the ECC operation is performed based at least in part on the parity bits for the metadata. ### Claim 7 (depends on 6) The apparatus of claim 6, wherein the interface controller is operable to cause the apparatus to: decode, as part of the ECC operation, a codeword comprising the parity bits and the metadata; and detect an error in the metadata based at least in part on decoding the codeword. ### Claim 8 (depends on 1) The apparatus of claim 1, wherein the interface controller is operable to cause the apparatus to: detect an error in the metadata based at least in part on the ECC operation; and correct the error detected in the metadata based at least in part on detecting the error, wherein the metadata is written to the register after correcting the error. ### Claim 9 (depends on 8) The apparatus of claim 8, wherein the interface controller is operable to cause the apparatus to: send an indication of the error to a controller included in the interface controller, the controller configured to manage commands for the volatile memory and commands for the non-volatile memory; and send the corrected metadata to the controller after sending the indication of the error. ### Claim 10 (depends on 1) The apparatus of claim 1, wherein the metadata is associated with a first bank of the memory array, and wherein the interface controller is operable to cause the apparatus to: read second metadata from the memory array, the second metadata associated with a second bank of the memory array; and write, based at least in part on performing a second ECC operation on the second metadata, the second metadata to a second register that is coupled with the memory array. ### Claim 11 A method, comprising: reading metadata from a memory array included in an interface controller coupled with volatile memory and a non-volatile memory, the metadata comprising information for operating the volatile memory as a cache for the non-volatile memory; performing an error correction code (ECC) operation on the metadata based at least in part on reading the metadata from the memory array; writing, based at least in part on performing the ECC operation, the metadata to a register that is coupled with the memory array; and writing the metadata from the register to the memory array. ### Claim 12 (depends on 11) The method of claim 11, further comprising: receiving an activate command for a row of a bank in the volatile memory, wherein the metadata is read from the memory array based at least in part on the activate command. ### Claim 13 (depends on 12) The method of claim 12, further comprising: receiving a precharge command for the row of the bank in the volatile memory, wherein the metadata is written to the memory array based at least in part on the precharge command. ### Claim 14 (depends on 12) The method of claim 12, further comprising: receiving a read command or a write command for the row after receiving the activate command; and updating the metadata in the register based at least in part on the read command or the write command. ### Claim 15 (depends on 12) The method of claim 12, further comprising: determining the bank, of the memory array, that is associated with the metadata based at least in part on the activate command, wherein the metadata is written to the register based at least in part on the register being configured for the bank. ### Claim 16 (depends on 11) The method of claim 11, further comprising: reading parity bits for the metadata from the memory array, wherein the ECC operation is performed based at least in part on the parity bits for the metadata. ### Claim 17 (depends on 16) The method of claim 16, further comprising: decoding, as part of the ECC operation, a codeword comprising the parity bits and the metadata; and detecting an error in the metadata based at least in part on decoding the codeword. ### Claim 18 (depends on 11) The method of claim 11, further comprising: detecting an error in the metadata based at least in part on the ECC operation; and correcting the error detected in the metadata based at least in part on detecting the error, wherein the metadata is written to the register after correcting the error. ### Claim 19 (depends on 18) The method of claim 18, further comprising: sending an indication of the error to a controller included in the interface controller, the controller for managing commands for the volatile memory and commands for the non-volatile memory; and sending the corrected metadata to the controller after sending the indication of the error. ### Claim 20 (depends on 11) The method of claim 11, wherein the metadata is associated with a first bank of the memory array, the method further comprising: reading second metadata from the memory array, the second metadata associated with a second bank of the memory array; and writing, based at least in part on performing a second ECC operation on the second metadata, the second metadata to a second register that is coupled with the memory array. ### Claim 21 An apparatus, comprising: a non-volatile memory; a volatile memory configured to operate as a cache for the non-volatile memory; and an interface controller coupled with the non-volatile memory and the volatile memory, the interface controller comprising: a static random access memory (SRAM) array configured to store metadata for operating the volatile memory as the cache; error correction code (ECC) logic coupled with the SRAM array and configured to perform an ECC operation on the metadata from the SRAM array; and a register, for a bank of the volatile memory, coupled with the ECC logic and configured to store metadata from the ECC logic, wherein the interface controller is configured to update the metadata in the register and communicate the metadata from the register to the SRAM array. ### Claim 22 (depends on 21) The apparatus of claim 21, wherein the interface controller comprises a set of registers coupled with the ECC logic, and wherein the set of registers includes the register and each register in the set of registers is associated with a respective bank of the volatile memory. ### Claim 23 (depends on 21) The apparatus of claim 21, further comprising: a controller coupled with the register and configured to control operations of the register. ### Claim 24 (depends on 21) The apparatus of claim 21, wherein the interface controller is configured to communicate the metadata from the SRAM array to the ECC logic, and wherein the interface controller is configured to communicate the metadata from the ECC logic to the register. ### Claim 25 (depends on 24) The apparatus of claim 24, wherein the interface controller is configured to communicate the metadata from the SRAM array to the ECC logic based at least in part on an activate command for a row of the bank, and wherein the interface controller is configured to communicate the metadata from the register to the SRAM array based at least in part on a precharge command for the row of the bank.