# US 2023/0055136 A1 · Systems and methods to flush data in persistent memory region to non-volatile memory using auxiliary processor

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- Number: US 2023/0055136 A1
- Document ID: US20230055136A1
- Status: Published application
- Kind: A1
- Application number: 17/406,961
- Filed: 2021-08-19
- Published: 2023-02-23
- Earliest claimed: 2021-08-19
- Assignees: Microsoft Technology Licensing, LLC
- Applicants: Microsoft Technology Licensing, LLC
- Inventors: Ravi MYSORE SHANTAMURTHY; Mallik BULUSU; Tom Long NGUYEN; Muhammad Ashfaq AHMED; Madhav Himanshubhai PANDYA
- Web page: https://patentgrep.com/patent/US20230055136A1

## CPC

- G06F 11/1441: {Resetting or repowering}
- G06F 12/0804: with main memory updating (G06F12/0806 takes precedence)
- G06F 11/2023: {Failover techniques}
- G06F 11/2038: {with a single idle spare processing component}
- G06F 11/2046: {where the redundant components share persistent storage (G06F11/2043 takes precedence)}
- G06F 11/2053: {where persistent mass storage functionality or persistent mass storage control functionality is redundant (error detection or correction in information storage based on relative movement between record carrier and transducer G11B20/18)}
- G06F 13/4027: {using bus bridges (G06F13/4022 takes precedence)}
- G06F 11/1612: {where the redundant component is persistent storage}
- G06F 11/2041: {with more than one idle spare processing component}
- G06F 11/3024: {where the computing system component is a central processing unit [CPU]}
- G06F 11/3409: {for performance assessment}
- G06F 2212/1032: Reliability improvement, data loss prevention, degraded operation etc
- Y02D 10/00: Energy efficient computing, e.g. low power processors, power management or thermal management
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- Y02D: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE

## Abstract

A computing system that enables data stored in a persistent memory region to be preserved when a processor fails can include volatile memory comprising the persistent memory region, non-volatile memory, and a system on a chip (SoC). The SoC can include a main processor that is communicatively coupled to both the volatile memory and the non-volatile memory. The SoC can also include an auxiliary processor that is communicatively coupled to both the volatile memory and the non-volatile memory. The SoC can also include instructions that are executable by the auxiliary processor to cause the data in the persistent memory region of the volatile memory to be transferred to the non-volatile memory in response to a failure of the main processor.

## Claims

### Claim 1

A computing system that enables data stored in a persistent memory region to be preserved when a processor fails, comprising:
volatile memory comprising the persistent memory region;
non-volatile memory; and
a system on a chip (SoC) being implemented on an integrated circuit, the SOC comprising:
a main processor on the integrated circuit that is communicatively coupled to both the volatile memory and the non-volatile memory;
an auxiliary processor on the integrated circuit that is communicatively coupled to both the volatile memory and the non-volatile memory; and
instructions that are executable by the auxiliary processor to cause the data in the persistent memory region of the volatile memory to be transferred to the non-volatile memory in response to a failure of the main processor.

### Claim 2 (depends on 1)

The computing system of claim 1, wherein the SoC further comprises:
a volatile memory interface on the integrated circuit that communicatively couples the volatile memory to the main processor and the auxiliary processor; and
a non-volatile memory interface on the integrated circuit that communicatively couples the non-volatile memory to the main processor and the auxiliary processor.

### Claim 3 (depends on 2)

The computing system of claim 2, wherein:
the SoC further comprises a bridge on the integrated circuit;
the volatile memory interface communicatively couples the volatile memory to the main processor and the auxiliary processor via the bridge; and
the non-volatile memory interface communicatively couples the non-volatile memory to the main processor and the auxiliary processor via the bridge.

### Claim 4 (depends on 1)

The computing system of claim 1, wherein the persistent memory region of the volatile memory comprises a software defined non-volatile dual in-line memory module (NVDIMM).

### Claim 5 (depends on 1)

The computing system of claim 1, wherein the SoC comprises an implementation of an Advanced Reduced Instruction Set Computer (RISC) Machines (ARM) architecture.

### Claim 6 (depends on 1)

The computing system of claim 1, wherein:
the main processor comprises a central processing unit (CPU); and
the auxiliary processor is responsible for monitoring the CPU and ensuring that the CPU is operating correctly.

### Claim 7 (depends on 1)

The computing system of claim 1, wherein the main processor and the auxiliary processor are both included on a same silicon die from which the SoC is formed.

### Claim 8 (depends on 1)

The computing system of claim 1, further comprising an interface that communicatively couples the main processor to the auxiliary processor.

### Claim 9 (depends on 1)

The computing system of claim 1, wherein:
the volatile memory is directly coupled to the SoC;
the computing system further comprises an additional SoC that is directly coupled to additional volatile memory;
the additional volatile memory comprises an additional persistent memory region; and
the instructions are additionally executable by the auxiliary processor to cause additional data in the additional persistent memory region to be transferred to the non-volatile memory in response to the failure of the main processor.

### Claim 10 (depends on 1)

The computing system of claim 1, wherein the SoC comprises a plurality of auxiliary processors.

### Claim 11

A system on a chip (SoC) implemented on an integrated circuit that enables data stored in a persistent memory region to be preserved when a processor fails, comprising:
a main processor on the integrated circuit that is communicatively coupled to volatile memory and non-volatile memory in a computing system, the volatile memory comprising the persistent memory region;
an auxiliary processor on the integrated circuit that is communicatively coupled to the volatile memory and the non-volatile memory; and
instructions that are executable by the auxiliary processor to cause data in the persistent memory region of the volatile memory to be transferred to the non-volatile memory in response to a failure of the main processor.

### Claim 12 (depends on 11)

The SoC of claim 11, further comprising:
a volatile memory interface on the integrated circuit that communicatively couples the volatile memory to the main processor and the auxiliary processor; and
a non-volatile memory interface on the integrated circuit that communicatively couples the non-volatile memory to the main processor and the auxiliary processor.

### Claim 13 (depends on 12)

The SoC of claim 12, wherein:
The SoC further comprises a bridge on the integrated circuit;
the volatile memory interface communicatively couples the volatile memory to the main processor and the auxiliary processor via the bridge; and
the non-volatile memory interface communicatively couples the non-volatile memory to the main processor and the auxiliary processor via the bridge.

### Claim 14 (depends on 11)

The SoC of claim 11, wherein the persistent memory region of the volatile memory comprises a software defined non-volatile dual in-line memory module (NVDIMM).

### Claim 15 (depends on 11)

The SoC of claim 11, wherein the SoC comprises an implementation of an Advanced Reduced Instruction Set Computer (RISC) Machines (ARM) architecture.

### Claim 16 (depends on 11)

The SoC of claim 11, wherein the main processor is communicatively coupled to the auxiliary processor via a high-speed bus.

### Claim 17

A method for enabling data stored in a persistent memory region in volatile memory to be preserved when a main processor on a computing system fails, the method being performed by an auxiliary processor that is located on a same system on a chip (SoC) as the main processor, the SoC being implemented on an integrated circuit, the method comprising:
receiving control of the computing system from the main processor on the integrated circuit in response to an error that makes the main processor inoperable;
causing the data in the persistent memory region in the volatile memory to be transferred to non-volatile memory; and
causing the computing system to be rebooted after the data has been transferred to the non-volatile memory.

### Claim 18 (depends on 17)

The method of claim 17, wherein:
the SoC comprises a volatile memory interface that communicatively couples the volatile memory to the main processor and the auxiliary processor;
the SoC further comprises a non-volatile memory interface that communicatively couples the non-volatile memory to the main processor and the auxiliary processor; and
causing the data to be transferred to the non-volatile memory comprises:
accessing the volatile memory via the volatile memory interface; and
accessing the non-volatile memory via the non-volatile memory interface.

### Claim 19 (depends on 17)

The method of claim 17, wherein receiving control of the computing system from the main processor comprises detecting an interrupt signal via an interface between the main processor and the auxiliary processor.

### Claim 20 (depends on 17)

The method of claim 17, further comprising reporting error information to a baseboard management controller (BMC).