# US 2023/0055073 A1 · Semiconductor structure manufacturing method and semiconductor structure > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2023/0055073 A1 - Document ID: US20230055073A1 - Status: Published application - Kind: A1 - Application number: 17/598,840 - Filed: 2021-06-29 - Published: 2023-02-23 - Earliest claimed: 2020-10-23 - Assignees: Changxin Memory Technologies, Inc. - Applicants: Changxin Memory Technologies, Inc. - Inventors: Lei YANG - Web page: https://patentgrep.com/patent/US20230055073A1 ## CPC - H10B 12/30: {DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells} - H10B 12/00: Dynamic random access memory [DRAM] devices - H10B 12/03: {Making the capacitor or connections thereto} - H10B 12/482: {Bit lines} - H10B: ELECTRONIC MEMORY DEVICES ## Abstract The embodiments of the present application belong to the technical field of semiconductor manufacturing, and relate to a semiconductor structure manufacturing method and a semiconductor structure. The semiconductor structure manufacturing method includes: the substrate is provided with a plurality of active area structures and a plurality of first hole structures arranged at intervals, first bonding pad structures are formed in the first hole structures, and the first bonding pad structures are electrically connected to the active area structures; and second bonding pad structures are formed on the first bonding pad structures, and the second bonding pad structures are connected to the first bonding pad structures, and connected to a capacitor structure. ## Claims ### Claim 1 A semiconductor structure manufacturing method, comprising: providing a substrate, wherein the substrate comprises a plurality of active area structures and a plurality of first hole structures distributed at intervals; forming first bonding pad structures in the first hole structures, wherein surfaces, away from the substrate, of the first bonding pad structures are flush with the substrate, and the first bonding pad structures are electrically connected to the active area structures; and forming second bonding pad structures on the first bonding pad structures, wherein the second bonding pad structures are connected to the first bonding pad structures, and the second bonding pad structures are connected to a capacitor structure. ### Claim 2 (depends on 1) The semiconductor structure manufacturing method of claim 1, wherein the forming first bonding pad structures in the first hole structures comprises: forming a barrier layer on side walls and bottom walls of the first hole structures and a surface of the substrate; forming a first conductive layer on the barrier layer, wherein the first hole structures are filled with the barrier layer and the first conductive layer; and removing part of the barrier layer and part of the first conductive layer to form the first bonding pad structures located in the first hole structures. ### Claim 3 (depends on 2) The semiconductor structure manufacturing method of claim 2, wherein the removing part of the barrier layer and part of the first conductive layer to form the first bonding pad structures located in the first hole structures comprises: removing the first conductive layer and the barrier layer outside the first hole structures to make surfaces, away from the substrate, of the first conductive layer and the barrier layer flush with the substrate; depositing a first supporting layer, a mask layer and a photoresist layer with patterns on the first conductive layer, the barrier layer and the substrate; and removing the part of the first conductive layer and the part of the barrier layer with the photoresist layer as a mask to form the first bonding pad structures. ### Claim 4 (depends on 3) The semiconductor structure manufacturing method of claim 3, wherein the removing the part of the first conductive layer and the part of the barrier layer with the photoresist layer as a mask to form the first bonding pad structures comprises: etching part of the mask layer with the photoresist layers as the mask to form the mask layer with patterns; removing the photoresist layer, and etching part of the first supporting layer with the mask layer as a mask to form the first supporting layer with patterns; and removing the mask layer, and etching the part of the first conductive layer and the part of the barrier layer with the first supporting layer as a mask to form the first bonding pad structures. ### Claim 5 (depends on 4) The semiconductor structure manufacturing method of claim 4, wherein forming second hole structures in the first supporting layer and the first hole structures while forming the first bonding pad structures. ### Claim 6 (depends on 5) The semiconductor structure manufacturing method of claim 5, wherein the forming second bonding pad structures on the first bonding pad structures, wherein the second bonding pad structures are connected to the first bonding pad structures comprises: depositing a second supporting layer in the second hole structures, wherein the second hole structures are filled with the second supporting layer; removing the first supporting layer, and forming third hole structures in the second supporting layer; and depositing a second conductive layer in the third hole structures, wherein the third hole structures are filled with the second conductive layer to form the second bonding pad structures. ### Claim 7 (depends on 6) The semiconductor structure manufacturing method of claim 6, wherein the depositing a second conductive layer in the third hole structures, wherein the third hole structures are filled with the second conductive layer to form the second bonding pad structures comprises: further covering the second supporting layer while filling the third hole structures by the second conductive layer; and removing the second conductive layer located outside the third hole structures after the second conductive layer are formed. ### Claim 8 (depends on 7) The semiconductor structure manufacturing method of claim 7, wherein the removing the second conductive layer located outside the third hole structures comprises: removing the second conductive layer located outside the third hole structures by a process of chemical-mechanical polishing. ### Claim 9 (depends on 6) The semiconductor structure manufacturing method of claim 6, wherein an etching selectivity ratio of a material of the first supporting layer to a material of the second supporting layer is larger than 100. ### Claim 10 (depends on 6) The semiconductor structure manufacturing method of claim 6, wherein a material of the first conductive layer is the same as a material of the second conductive layer. ### Claim 11 (depends on 10) The semiconductor structure manufacturing method of claim 10, wherein both the material of the first conductive layer and the material of the second conductive layer are tungsten. ### Claim 12 (depends on 3) The semiconductor structure manufacturing method of claim 3, wherein the removing the first conductive layer and the barrier layer outside the first hole structures to make the surfaces, away from the substrate, of the first conductive layer and the barrier layer flush with the substrate comprises: removing the first conductive layer and the barrier layer outside the first hole structures by a process of chemical-mechanical polishing. ### Claim 13 (depends on 2) The semiconductor structure manufacturing method of claim 2, wherein a material of the barrier layer comprises titanium nitride. ### Claim 14 (depends on 1) The semiconductor structure manufacturing method of claim 1, wherein the substrate further comprises bit line structures and capacitor contact structures, the first bonding pad structures are connected to the capacitor contact structures, and the capacitor contact structures are connected to the active area structures. ### Claim 15 (depends on 1) The semiconductor structure manufacturing method of claim 1, after the forming second bonding pad structures, further comprising: forming the capacitor structure, wherein the capacitor structure is connected to the second bonding pad structures. ### Claim 16 (depends on 1) A semiconductor structure, manufactured by the semiconductor structure manufacturing method of claim 1.