# US 2023/0055062 A1 · Semiconductor device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2023/0055062 A1 - Document ID: US20230055062A1 - Status: Published application - Kind: A1 - Application number: 17/796,903 - Filed: 2021-02-08 - Published: 2023-02-23 - Earliest claimed: 2020-02-21 - Assignees: Semiconductor Energy Laboratory Co., Ltd. - Applicants: Semiconductor Energy Laboratory Co., Ltd. - Inventors: Yuki OKAMOTO; Munehiro KOZUMA; Tatsuya ONUKI - Web page: https://patentgrep.com/patent/US20230055062A1 ## CPC - G06F 7/5443: {Sum of products (for applications thereof, see the relevant places, e.g. G06F17/10, H03H17/00)} - G06F 12/00: Accessing, addressing or allocating within memory systems or architectures (digital input from, or digital output to record carriers, e.g. to disk storage units, G06F3/06) - G06F 17/10: Complex mathematical operations {(function generation by table look-up G06F1/03; evaluation of elementary functions by calculation G06F7/544)} - G11C 11/405: with three charge-transfer gates, e.g. MOS transistors, per cell - H10B 12/00: Dynamic random access memory [DRAM] devices - H10B 41/70: the floating gate being an electrode shared by two or more components - H10D 30/021: {of FETs having insulated gates [IGFET]} - H10D 30/6734: {having gate electrodes arranged on both top and bottom sides of the channel, e.g. dual-gate TFTs} - H10D 30/6755: {Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate} - H10D 30/68: Floating-gate IGFETs - H10D 30/69: IGFETs having charge trapping gate insulators, e.g. MNOS transistors - H10D 86/423: {comprising semiconductor materials not belonging to the Group IV, e.g. InGaZnO} - H10D 86/481: {integrated with passive devices, e.g. auxiliary capacitors} - H10D 86/60: wherein the TFTs are in active matrices - H10D 87/00: Integrated devices comprising both bulk components and either SOI or SOS components on the same substrate - H10D 88/00: Three-dimensional [3D] integrated devices - Y02D 10/00: Energy efficient computing, e.g. low power processors, power management or thermal management - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - G11C: STATIC STORES (semiconductor memory devices H10B) - H10B: ELECTRONIC MEMORY DEVICES - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES - Y02D: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE ## Abstract A semiconductor device with a novel structure is provided. A plurality of memory circuits, a switching circuit, and an arithmetic circuit are included. Each of the plurality of memory circuits has a function of retaining weight data and a function of outputting the weight data to a first wiring. The switching circuit has a function of switching a conduction state between any one of the plurality of first wirings and a second wiring. The arithmetic circuit has a function of performing arithmetic processing using input data and the weight data supplied to the second wiring. The memory circuits are provided in a first layer. The switching circuit and the arithmetic circuit are provided in a second layer. The first layer is provided in a layer different from the second layer. ## Claims ### Claim 1 A semiconductor device comprising a plurality of memory circuits, a switching circuit, and an arithmetic circuit, wherein each of the plurality of memory circuits is configured to retain weight data, wherein the switching circuit is configured to switch a conduction state between any one of the memory circuits and the arithmetic circuit, wherein the plurality of memory circuits is provided in a first layer, wherein the switching circuit and the arithmetic circuit are provided in a second layer, and wherein the first layer is a layer different from the second layer. ### Claim 2 A semiconductor device comprising a plurality of memory circuits, a switching circuit, and an arithmetic circuit, wherein each of the plurality of memory circuits is configured to retain weight data and is configured to output the weight data to a first wiring, wherein the switching circuit is configured to switch a conduction state between any one of the plurality of first wirings and the arithmetic circuit, wherein the plurality of memory circuits is provided in a first layer, wherein the switching circuit and the arithmetic circuit are provided in a second layer, and wherein the first layer is a layer different from the second layer. ### Claim 3 A semiconductor device comprising a plurality of memory circuits, a switching circuit, and an arithmetic circuit, wherein each of the plurality of memory circuits is configured to retain weight data and is configured to output the weight data to a first wiring, wherein the switching circuit is configured to switch a conduction state between any one of the plurality of first wirings and a second wiring, wherein the arithmetic circuit is configured to perform arithmetic processing using input data and the weight data supplied to the second wiring, wherein the plurality of memory circuits is provided in a first layer, wherein the switching circuit and the arithmetic circuit are provided in a second layer, and wherein the first layer is a layer different from the second layer. ### Claim 4 (depends on 3) The semiconductor device according to claim 3, wherein the second wiring comprises a wiring provided substantially parallel to a substrate surface. ### Claim 5 (depends on 2) The semiconductor device according to claim 2, wherein the first wiring comprises a wiring provided substantially perpendicular to the substrate surface. ### Claim 6 (depends on 1) The semiconductor device according to claim 1, wherein the first layer comprises a first transistor, and wherein the first transistor comprises a semiconductor layer comprising a metal oxide in a channel formation region. ### Claim 7 (depends on 6) The semiconductor device according to claim 6, wherein the metal oxide comprises In, Ga, and Zn. ### Claim 8 (depends on 1) The semiconductor device according to claim 1, wherein the second layer comprises a second transistor, and wherein the second transistor comprises a semiconductor layer comprising silicon in a channel formation region. ### Claim 9 (depends on 1) The semiconductor device according to claim 1, wherein the arithmetic circuit is configured to perform product-sum operation. ### Claim 10 (depends on 1) The semiconductor device according to claim 1, wherein the first layer is provided to be stacked over the second layer. ### Claim 11 (depends on 1) The semiconductor device according to claim 1, wherein the weight data is data having a first number of bits, wherein the weight data is obtained by converting weight data having a second number of bits optimized with learning data, and wherein the first number of bits is smaller than the second number of bits. ### Claim 12 (depends on 2) The semiconductor device according to claim 2, wherein the first layer comprises a first transistor, and wherein the first transistor comprises a semiconductor layer comprising a metal oxide in a channel formation region. ### Claim 13 (depends on 12) The semiconductor device according to claim 12, wherein the metal oxide comprises In, Ga, and Zn. ### Claim 14 (depends on 2) The semiconductor device according to claim 2, wherein the second layer comprises a second transistor, and wherein the second transistor comprises a semiconductor layer comprising silicon in a channel formation region. ### Claim 15 (depends on 2) The semiconductor device according to claim 2, wherein the arithmetic circuit is configured to perform product-sum operation. ### Claim 16 (depends on 2) The semiconductor device according to claim 2, wherein the first layer is provided to be stacked over the second layer. ### Claim 17 (depends on 2) The semiconductor device according to claim 2, wherein the weight data is data having a first number of bits, wherein the weight data is obtained by converting weight data having a second number of bits optimized with learning data, and wherein the first number of bits is smaller than the second number of bits. ### Claim 18 (depends on 3) The semiconductor device according to claim 3, wherein the first wiring comprises a wiring provided substantially perpendicular to the substrate surface. ### Claim 19 (depends on 3) The semiconductor device according to claim 3, wherein the first layer comprises a first transistor, and wherein the first transistor comprises a semiconductor layer comprising a metal oxide in a channel formation region. ### Claim 20 (depends on 19) The semiconductor device according to claim 19, wherein the metal oxide comprises In, Ga, and Zn. ### Claim 21 (depends on 3) The semiconductor device according to claim 3, wherein the second layer comprises a second transistor, and wherein the second transistor comprises a semiconductor layer comprising silicon in a channel formation region. ### Claim 22 (depends on 3) The semiconductor device according to claim 3, wherein the arithmetic circuit is configured to perform product-sum operation. ### Claim 23 (depends on 3) The semiconductor device according to claim 3, wherein the first layer is provided to be stacked over the second layer. ### Claim 24 (depends on 3) The semiconductor device according to claim 3, wherein the weight data is data having a first number of bits, wherein the weight data is obtained by converting weight data having a second number of bits optimized with learning data, and wherein the first number of bits is smaller than the second number of bits.