# US 2023/0055058 A1 · Wafer defect test apparatus, wafer defect test system, wafer test method and fabrication method of a wafer

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- Number: US 2023/0055058 A1
- Document ID: US20230055058A1
- Status: Published application
- Kind: A1
- Application number: 17/680,958
- Filed: 2022-02-25
- Published: 2023-02-23
- Earliest claimed: 2021-08-23
- Assignees: Samsung Electronics Co., Ltd.
- Applicants: Samsung Electronics Co., Ltd.
- Inventors: SUNG HEE LEE; JAE YOON KIM; JUNG HWAN MOON; JUNG HOON BAK; KYU-BAlK CHANG; JAE HOON JEONG; MIN KYOUNG JOO
- Web page: https://patentgrep.com/patent/US20230055058A1

## CPC

- G05B 19/41875: {characterised by quality surveillance of production}
- G06N 5/02: Knowledge representation; Symbolic representation
- G05B 2219/32368: Quality control
- G05B 2219/45031: Manufacturing semiconductor wafers
- G06N 20/00: Machine learning
- G05B: CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS (systems for controlling or regulating non-electric variables G05D; systems for regulating electric or magnetic variables G05F; control devices or systems insofar as characterised by mechanical features only G05G)
- G06N: COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS

## Abstract

A wafer defect test apparatus in which a defect prediction performance is improved and a simulation time is shortened is provided. The wafer defect test apparatus comprises a wafer variable generator which receives a first structural measurement data and a first process condition data of a first wafer, and a second structural measurement data and a second process condition data of a second wafer, generates a first process variable and a second process variable based on the first structural measurement data and the first process condition data, and generates a third process variable and a fourth process variable based on the second structural measurement data and the second process condition data, an abnormal wafer index generating circuit which generates a first wafer vector of the first process variable and second process variable, generates a second wafer vector of the third process variable and fourth process variable, calculates a first Euclidean distance between the first wafer vector and the second wafer vector, calculates a first Cosine distance between the first wafer vector and the second wafer vector, and generates a first abnormal wafer index of the first wafer based on a product of the first Euclidean distance and the first Cosine distance, and a prediction model generating circuit which receives a first characteristic variable which is a test result of the first wafer, and generates a wafer defect prediction model through a regression based on the first process variable, the second process variable, the first characteristic variable, and the first abnormal wafer index.

## Claims

### Claim 1

A wafer defect test apparatus, comprising:
a wafer variable generator which receives a first structural measurement data and a first process condition data of a first wafer, and a second structural measurement data and a second process condition data of a second wafer, generates a first process variable and a second process variable based on the first structural measurement data and the first process condition data, and generates a third process variable and a fourth process variable based on the second structural measurement data and the second process condition data;
an abnormal wafer index generating circuit which generates a first wafer vector of the first process variable and second process variable, generates a second wafer vector of the third process variable and the fourth process variable, calculates a first Euclidean distance between the first wafer vector and the second wafer vector, calculates a first Cosine distance between the first wafer vector and the second wafer vector, and generates a first abnormal wafer index of the first wafer based on a product of the first Euclidean distance and the first Cosine distance; and
a prediction model generating circuit which receives a first characteristic variable which is a test result of the first wafer, and generates a wafer defect prediction model through a regression based on the first process variable, the second process variable, the first characteristic variable, and the first abnormal wafer index.

### Claim 2 (depends on 1)

The wafer defect test apparatus of claim 1, wherein the first abnormal wafer index is proportional to the product of the first Euclidean distance and the first Cosine distance.

### Claim 3 (depends on 1)

The wafer defect test apparatus of claim 1, wherein the wafer variable generator generates a fifth process variable and a sixth process variable, based on a third structural measurement data and a third process condition data of a third wafer different from the first wafer and second wafer, and
the abnormal wafer index generating circuit generates a third wafer vector of the fifth process variable and the sixth process variable.

### Claim 4 (depends on 3)

The wafer defect test apparatus of claim 3, wherein the abnormal wafer index generating circuit calculates a second Euclidean distance between the first wafer vector and the third wafer vector, calculates a second Cosine distance between the first wafer vector and the third wafer vector, and generates a second abnormal wafer index of the first wafer based on a product of the second Euclidean distance and the second Cosine distance.

### Claim 5 (depends on 4)

The wafer defect test apparatus of claim 4, wherein the prediction model generating circuit generates a wafer defect prediction model, based on the first process variable, the second process variable, the first characteristic variable, the first abnormal wafer index, and the second abnormal wafer index.

### Claim 6 (depends on 1)

The wafer defect test apparatus of claim 1, wherein the abnormal wafer index generating circuit receives a second characteristic variable, which is a prediction test result of the first wafer, and generates a fourth wafer vector of at least two among the first process variable, the second process variable, and the second characteristic variable.

### Claim 7 (depends on 6)

The wafer defect test apparatus of claim 6, wherein the abnormal wafer index generating circuit generates a third abnormal wafer index of the first wafer, based on the product of an Euclidean distance and a Cosine distance between the second wafer vector and the fourth wafer vector.

### Claim 8 (depends on 1)

The wafer defect test apparatus of claim 1, wherein the prediction model generating circuit generates the wafer defect prediction model, using the first process variable, the second process variable, and the first abnormal wafer index as an input, and using the first characteristic variable as an output.

### Claim 9 (depends on 1)

The wafer defect test apparatus of claim 1, further comprising:
an abnormal wafer detector which tests whether the first wafer is defective based on the wafer defect prediction model and the first abnormal wafer index.

### Claim 10

(canceled)

### Claim 11

A wafer defect test system, comprising:
a monitoring apparatus which monitors a first wafer, a second wafer, and a third wafer being fabricated; and
a computing apparatus connected to the monitoring apparatus,
wherein the monitoring apparatus monitors the first wafer to generate a first process variable and a second process variable,
the monitoring apparatus monitors the second wafer to generate a third process variable and a fourth process variable,
the monitoring apparatus monitors the third wafer to generate a fifth process variable and a sixth process variable,
the computing apparatus generates a first wafer vector of the first process variable and the second process variable,
the computing apparatus generates a second wafer vector of the third process variable and the fourth process variable,
the computing apparatus generates a third wafer vector of the fifth process variable and the sixth process variable,
the computing apparatus calculates a first Euclidean distance between the first wafer vector and the second wafer vector,
the computing apparatus calculates a first Cosine distance between the first wafer vector and the second wafer vector,
the computing apparatus calculates a second Euclidean distance between the first wafer vector and the third wafer vector,
the computing apparatus calculates a second Cosine distance between the first wafer vector and the third wafer vector,
the computing apparatus calculates a third Euclidean distance between the second wafer vector and the third wafer vector,
the computing apparatus calculates a third Cosine distance between the second wafer vector and the third wafer vector,
the computing apparatus generates a first abnormal wafer index of the first wafer, based on a product of the first Euclidean distance and the first Cosine distance and a product of the second Euclidean distance and the second Cosine distance,
the computing apparatus generates a second abnormal wafer index of the second wafer, based on the product of the first Euclidean distance and the first Cosine distance and a product of the third Euclidean distance and the third Cosine distance,
the computing apparatus generates a third abnormal wafer index of the third wafer, based on a product of the second Euclidean distance and the second Cosine distance and the product of the third Euclidean distance and the third Cosine distance, and
the computing apparatus predicts defective wafers among the first wafer to third wafer, using the first abnormal wafer index to the third abnormal wafer index.

### Claim 12 (depends on 11)

The wafer defect test system of claim 11, wherein the first abnormal wafer index to the third abnormal wafer index have different values from each other, and a value of the first abnormal wafer index is larger than values of the second abnormal wafer index and the third abnormal wafer index.

### Claim 13 (depends on 12)

The wafer defect test system of claim 12, wherein the computing apparatus predicts the first wafer as defect, using the first abnormal wafer index.

### Claim 14 (depends on 11)

The wafer defect test system of claim 11, wherein the computing apparatus generates a wafer defect prediction model based on the first process variable to the sixth process variable and the first abnormal wafer index to the third abnormal wafer index, and predicts a defective wafer among the first wafer to the third wafer, using the wafer defect prediction model.

### Claim 15 (depends on 11)

The wafer defect test system of claim 11, wherein the first abnormal wafer index is proportional to a sum of the product of the first Euclidean distance and the first Cosine distance and the product of the second Euclidean distance and the second Cosine distance,
the second abnormal wafer index is proportional to the sum of the product of the first Euclidean distance and the first Cosine distance and the product of the third Euclidean distance and the third Cosine distance, and
the third abnormal wafer index is proportional to the sum of the product of the second Euclidean distance and the second Cosine distance and the product of the third Euclidean distance and the third Cosine distance.

### Claim 16 (depends on 11)

The wafer defect test system of claim 11, further comprising:
a test apparatus which tests the first wafer to the third wafer,
wherein the test apparatus tests the first wafer to generate a first characteristic variable,
the test apparatus tests the second wafer to generate a second characteristic variable, and
the test apparatus tests the third wafer to generate a third characteristic variable.

### Claim 17 (depends on 16)

The wafer defect test system of claim 16, wherein the computing apparatus generates a wafer defect prediction model based on the first characteristic variable to the third characteristic variable, the first process variable to the sixth process variable, and the first abnormal wafer index to the third abnormal wafer index, and predicts defective wafers among the first wafer to the third wafer, using the wafer defect prediction model.

### Claim 18

A method for fabricating a wafer, the method comprising:
fabricating a first wafer, a second wafer and a third wafer different from each other;
generating a wafer defect prediction model, using the fabricated first wafer and second wafer; and
testing for a defect of the third wafer, using the wafer defect prediction model,
wherein generating the wafer defect prediction model includes
monitoring the first wafer to generate a first wafer vector of a first process variable and a second process variable,
monitoring the second wafer to generate a second wafer vector of a third process variable and a fourth process variable,
calculating a first Euclidean distance between the first wafer vector and the second wafer vector,
calculating a first Cosine distance between the first wafer vector and the second wafer vector,
generating a first abnormal wafer index of the first wafer based on a product of the first Euclidean distance and the first Cosine distance,
generating a first characteristic variable by testing the fabricated first wafer, and
generating a wafer defect prediction model through regression based on the first process variable, the second process variable, the first characteristic variable, and the first abnormal wafer index.

### Claim 19 (depends on 18)

The method for fabricating the wafer of claim 18, wherein testing for the defect of the third wafer using the wafer defect prediction model includes
monitoring the third wafer to generate a third wafer vector of a fifth process variable and a sixth process variable,
generating a second abnormal wafer index which is a sum of a product of a second Euclidean distance and a second Cosine distance between the third wafer vector and the first wafer vector, and a product of a third Euclidean distance and a third Cosine distance between the third wafer vector and the second wafer vector, and
detecting whether the third wafer is defective, based on the fifth process variable, the sixth process variable, the second abnormal wafer index, and the wafer defect prediction model.

### Claim 20 (depends on 19)

The method for fabricating the wafer of claim 19, wherein the third wafer is fabricated based on whether the third wafer is defective.

### Claim 21 (depends on 19)

The method for fabricating the wafer of claim 19, further comprising:
performing feedback on the fabrication of a fourth wafer different from the first wafer to the third wafer based on whether the third wafer is defective.

### Claim at position 22

22-25. (canceled)