# US 2023/0054984 A1 · Semiconductor package

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 2023/0054984 A1
- Document ID: US20230054984A1
- Status: Published application
- Kind: A1
- Application number: 17/722,616
- Filed: 2022-04-18
- Published: 2023-02-23
- Earliest claimed: 2021-08-18
- Assignees: Samsung Electronics Co., Ltd.
- Applicants: Samsung Electronics Co., Ltd.
- Inventors: Joonsung KIM
- Web page: https://patentgrep.com/patent/US20230054984A1

## CPC

- H10W 90/00: Package configurations
- H10W 70/09: extending onto an encapsulation that laterally surrounds the chip or wafer, e.g. fan-out wafer level package [FOWLP] RDLs
- H10W 70/611: {for connecting multiple chips together}
- H10W 70/614: {the multiple chips being integrally enclosed}
- H10W 70/65: Shapes or dispositions of interconnections
- H10W 70/685: comprising multiple insulating layers
- H10W 72/20: Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
- H10W 90/401: {characterised by multiple insulating or insulated package substrates, interposers or RDLs}
- H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts}
- H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40)
- H10W 72/30: Die-attach connectors
- H10W 72/823: {Interconnections through encapsulations, e.g. pillars through molded resin on a lateral side a chip}
- H10W 90/722: {between stacked chips}
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/732: {between stacked chips}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor package includes a connection substrate on a package substrate and has an opening that penetrates therethrough. A chip stack is on the package substrate and in the opening. A redistribution layer is on the connection substrate and the chip stack. An upper semiconductor chip is on first redistribution pads of the redistribution layer. External terminals are on a bottom surface of the package substrate. The chip stack includes a first semiconductor chip on substrate pads of the package substrate, and a second semiconductor chip on the first semiconductor chip and second redistribution pads of the redistribution layer. The redistribution layer includes a first region that overlaps the upper semiconductor chip and a second region beside the upper semiconductor chip. The first redistribution pads are on the first region. The second redistribution pads are on the second region.

## Claims

### Claim 1

A semiconductor package, comprising:
a package substrate;
a connection substrate on the package substrate and an opening that penetrates the connection substrate;
a chip stack on the package substrate and in the opening of the connection substrate;
a redistribution layer on the connection substrate and the chip stack;
an upper semiconductor chip on first redistribution pads of the redistribution layer; and
a plurality of external terminals on a bottom surface of the package substrate,
wherein the chip stack includes
a first semiconductor chip on substrate pads of the package substrate; and
a second semiconductor chip on the first semiconductor chip and on second redistribution pads of the redistribution layer,
wherein the redistribution layer includes
a first region that overlaps the upper semiconductor chip; and
a second region beside of the upper semiconductor chip,
wherein the first redistribution pads are on the first region, and
wherein the second redistribution pads are on the second region.

### Claim 2 (depends on 1)

The semiconductor package of claim 1, wherein
the upper semiconductor chip has a width less than a width of the second semiconductor chip,
the upper semiconductor chip is within a perimeter of the second semiconductor chip, and
the second region surrounds the first region.

### Claim 3 (depends on 1)

The semiconductor package of claim 1, wherein
the upper semiconductor chip runs across the second semiconductor chip in a first direction parallel to a top surface of the redistribution layer, and
the second region is on at least one side of the first region in a second direction that intersects the first direction.

### Claim 4 (depends on 1)

The semiconductor package of claim 1, wherein
the upper semiconductor chip is offset from the second semiconductor chip in a first direction parallel to a top surface of the redistribution layer, and
the first region is in the first direction from the second region.

### Claim 5 (depends on 1)

The semiconductor package of claim 1, wherein
at least one of the first redistribution pads overlap the second semiconductor chip, and
the second redistribution pads do not overlap the upper semiconductor chip.

### Claim 6 (depends on 1)

The semiconductor package of claim 1, wherein
the upper semiconductor chip includes a first active surface that faces the redistribution layer, and first chip terminals of the upper semiconductor chip are connected to the first redistribution pads between the upper semiconductor chip and the redistribution layer, and
the second semiconductor chip includes a second active surface that faces the redistribution layer, and second chip terminals of the second semiconductor chip are connected to the second redistribution pads between the second semiconductor chip and the redistribution layer.

### Claim 7

(canceled)

### Claim 8

(canceled)

### Claim 9 (depends on 1)

The semiconductor package of claim 1, wherein the redistribution layer includes:
a dielectric pattern;
the first redistribution pads and the second redistribution pads on a top surface of the dielectric pattern; and
a protection layer on the top surface of the dielectric pattern, the protection layer that covers the first redistribution pads and the second redistribution pads.

### Claim at position 10

-12. (canceled)

### Claim 13 (depends on 1)

The semiconductor package of claim 1, wherein the redistribution layer includes:
a dielectric pattern;
the first redistribution pads and the second redistribution pads that are on a top surface of the dielectric pattern;
a protection layer on a top surface of the dielectric pattern and that covers the first redistribution pads and the second redistribution pads; and
a third redistribution pad on the protection layer and connected through a vertical connection via to the first redistribution pad,
wherein upper chip terminal of the upper semiconductor chip is directly connected to the third redistribution pad, and
wherein a second chip terminal of the second semiconductor chip penetrates the dielectric pattern to be directly connected to the second redistribution pad.

### Claim at position 12

-16. (canceled)

### Claim 17 (depends on 1)

The semiconductor package of claim 1, wherein
the upper semiconductor chip is provided in plural, and
the second region of the redistribution layer is between the plurality of upper semiconductor chips.

### Claim 18

A semiconductor package, comprising:
a package substrate;
a redistribution layer on the package substrate;
a connection substrate that connects the package substrate to the redistribution layer, the connection substrate having an opening that vertically penetrates the connection substrate;
a first semiconductor chip in the opening of the connection substrate, a first active surface of the first semiconductor chip being in contact with the package substrate;
a second semiconductor chip in the opening of the connection substrate, a second active surface of the second semiconductor chip being in contact with the redistribution layer; and
a third semiconductor chip on the redistribution layer,
wherein the redistribution layer includes
a dielectric pattern;
a first redistribution pad and a second redistribution pad that are on a top surface of the dielectric pattern;
a first redistribution via that vertically penetrates the dielectric pattern to connect the first redistribution pad to a chip pad of the second semiconductor chip; and
a protection layer on the top surface of the dielectric pattern, the protection layer covers the first redistribution pad and the second redistribution pad,
wherein the third semiconductor chip is directly connected through a chip terminal to the second redistribution pad exposed on the protection layer, and
wherein the first redistribution pad and the second redistribution pad are at a same level from the package substrate.

### Claim 19 (depends on 18)

The semiconductor package of claim 18, wherein the redistribution layer has:
a first region on which the first redistribution pad is provided; and
a second region on which the second redistribution pad is provided,
wherein the second region vertically overlaps the third semiconductor chip.

### Claim at position 16

-23. (canceled)

### Claim 24 (depends on 18)

The semiconductor package of claim 18, wherein
the first redistribution pad includes a plurality of first redistribution pads and the second redistribution pad includes a plurality of second redistribution pads,
at least one of the plurality of first redistribution pads is above the second semiconductor chip and are out from below the third semiconductor chip, and
the plurality of second redistribution pads are between the second semiconductor chip and the third semiconductor chip.

### Claim 25 (depends on 18)

The semiconductor package of claim 18, wherein the redistribution layer further includes:
a redistribution pattern connected to the first redistribution pad and the second redistribution pattern; and
a second redistribution via that vertically penetrates the dielectric pattern to connect the redistribution pattern to the connection substrate,
wherein the redistribution pattern is at a same level from the package substrate as that of the first redistribution pad and that of the second redistribution pad.

### Claim 26

(canceled)

### Claim 27 (depends on 18)

The semiconductor package of claim 18, wherein a portion of the dielectric pattern included in the redistribution layer extends into the opening of the connection substrate to fill a space between the connection substrate and the first and second semiconductor chips.

### Claim 28

A semiconductor package, comprising:
a package substrate;
a first semiconductor chip on the package substrate;
a redistribution layer on the first semiconductor chip;
a second semiconductor chip mounted on a first surface of the redistribution layer;
a third semiconductor chip mounted on a second surface of the redistribution layer; and
a connection member between the package substrate and the redistribution layer and beside of the first semiconductor chip, the connection member connects the package substrate to the redistribution layer,
wherein the redistribution layer includes a first redistribution pad and a second redistribution pad that are at a same level from the package substrate,
wherein the second semiconductor chip is directly connected through a first terminal on the first redistribution pad,
wherein the third semiconductor chip is directly connected through a second terminal on the second redistribution pad,
wherein the redistribution layer includes a first region on which the first redistribution pad is provided and a second region on which the second redistribution pad is provided,
wherein the second region vertically overlaps both of the second semiconductor chip and the third semiconductor chip, and
wherein the first region is laterally spaced apart from the third semiconductor chip.

### Claim 29 (depends on 28)

The semiconductor package of claim 28, wherein
the first surface of the redistribution layer is directed toward the package substrate, and
an inactive surface of the second semiconductor chip is in contact with an inactive surface of the first semiconductor chip.

### Claim 30

(canceled)

### Claim 31 (depends on 28)

The semiconductor package of claim 28, wherein
the third semiconductor chip has a width less than a width of the second semiconductor chip, and the third semiconductor chip is within a perimeter of the second semiconductor chip, and
the first region surrounds the second region.

### Claim 32 (depends on 28)

The semiconductor package of claim 28, wherein the redistribution layer includes:
a dielectric pattern;
the first redistribution pad and the second redistribution pad that are on a top surface of the dielectric pattern; and
a protection layer on the top surface of the dielectric pattern, the protection layer covers the first redistribution pad and the second redistribution pad.

### Claim 33

(canceled)

### Claim 34 (depends on 28)

The semiconductor package of claim 28, further comprising a dielectric layer that fills a space between the package substrate and the redistribution layer,
wherein the connection member includes a through electrode that vertically penetrates the dielectric layer.

### Claim 35 (depends on 28)

The semiconductor package of claim 28, further comprising:
a connection substrate between the package substrate and the redistribution layer and having an opening that penetrates the connection substrate, the first semiconductor chip and the second semiconductor chip being in the opening; and
a dielectric layer that fills a space between the connection substrate and the first and second semiconductor chips in the opening,
wherein the connection member includes a substrate wiring pattern in the connection substrate.

### Claim 36

(canceled)