# US 2023/0054951 A1 · Measuring a change in voltage

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- Number: US 2023/0054951 A1
- Document ID: US20230054951A1
- Status: Published application
- Kind: A1
- Application number: 17/407,725
- Filed: 2021-08-20
- Published: 2023-02-23
- Earliest claimed: 2021-08-20
- Assignees: STMicroelectronics S.r.l.
- Applicants: STMicroelectronics S.r.l.
- Inventors: Davide Argento; Orazio Pennisi; Stefano Castorina; Vanni Poletto; Matteo Landini; Andrea Maino
- Web page: https://patentgrep.com/patent/US20230054951A1

## CPC

- G01R 19/10: Measuring sum, difference or ratio
- G01R 27/2605: {Measuring capacitance (capacitive sensors G01D5/24)}
- B60R 21/0173: {Diagnostic or recording means therefor}
- G01R 31/006: {on road vehicles, e.g. automobiles or trucks (testing of ignition installations peculiar to internal combustion engines F02P17/00)}
- G01R 31/64: Testing of capacitors
- H03M 1/124: {Sampling or signal conditioning arrangements specially adapted for A/D converters}
- H03M 3/464: {Details of the digital/analogue conversion in the feedback path}
- H03M 3/494: {Sampling or signal conditioning arrangements specially adapted for delta-sigma type analogue/digital conversion systems}
- G01R: MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES (indicating correct tuning of resonant circuits H03J3/12)
- B60R: VEHICLES, VEHICLE FITTINGS, OR VEHICLE PARTS, NOT OTHERWISE PROVIDED FOR
- H03M: CODING; DECODING; CODE CONVERSION IN GENERAL (using fluidic means F15C4/00; optical analogue/digital converters G02F7/00; coding, decoding or code conversion, specially adapted for particular applications, see the relevant subclasses, e.g. G01D, G01R, G06F, G06T, G09G, G10L, G11B, G11C, H04B, H04L, H04M, H04N; ciphering or deciphering for cryptography or other purposes involving the need for secrecy G09C)

## Abstract

A system and method is provided for measuring a voltage drop at a node. In embodiments, a circuit includes an analog-to-digital converter, a current sink, and a controller. The input of the analog-to-digital converter and the input of the current sink is coupled to the node to be measured. A set point for the current sink is determined. The output of the analog-to-digital converter during the voltage drop is sampled. And a relative voltage drop value is computed by subtracting the sampled output of the analog-to-digital converter during the voltage drop from a sampled output of the analog-to-digital converter during a steady-state condition. The current sink operating at the set point during the steady-state condition and during the voltage drop.

## Claims

### Claim 1

A method for measuring a voltage drop at a node, the method comprising:
having a circuit comprising an analog-to-digital converter, a current sink, and a controller, an input of the analog-to-digital converter and an input of the current sink coupled to the node;
determining a set point for the current sink;
sampling an output of the analog-to-digital converter during the voltage drop; and
computing a relative voltage drop value comprising subtracting the sampled output of the analog-to-digital converter during the voltage drop from a sampled output of the analog-to-digital converter during a steady-state condition, the current sink operating at the set point during the steady-state condition and during the voltage drop.

### Claim 2 (depends on 1)

The method of claim 1, wherein the determining the set point for the current sink comprises:
sampling a first output of the analog-to-digital converter during a second steady-state condition, the current sink disabled during the second steady-state condition; and
selectively adjusting an amount of current sunk through the current sink until the output of the analog-to-digital converter is at a targeted value relative to the first output.

### Claim 3 (depends on 2)

The method of claim 2, wherein selectively adjusting the amount of current sunk through the current sink comprises:
monitoring the output of the analog-to-digital converter;
adjusting the amount of current sunk by a control signal generated by the controller based on monitoring the output of the analog-to-digital converter; and
communicating the control signal to a digital-to-analog converter (DAC) of the current sink.

### Claim 4 (depends on 2)

The method of claim 2, wherein the targeted value corresponds to a ratio between 9.9 and 10.1 percent.

### Claim 5 (depends on 1)

The method of claim 1, wherein the voltage drop comprises enabling a discharge switch coupled to the node such that a voltage at the node drops in value.

### Claim 6 (depends on 1)

The method of claim 1, further comprising computing a voltage drop value at the node based on a linear relationship between the voltage drop and the relative voltage drop value.

### Claim 7 (depends on 1)

The method of claim 1, wherein the set point is chosen to prevent the analog-to-digital converter from saturating.

### Claim 8 (depends on 1)

The method of claim 1, wherein the node is a node of a reserve capacitor of a supplemental restraint system (SRS) in a vehicle.

### Claim 9

A circuit for measuring a voltage drop at a node, the circuit comprising:
an analog-to-digital converter (ADC) coupled to the node;
a current sink coupled to the node and an input of the analog-to-digital converter, the current sink configured to be adjusted via a control signal to selectively adjust an amount of current sunk through the current sink; and
a controller coupled to an output of the analog-to-digital converter and a control input of the current sink, the controller configured to:
determine a set point for the current sink;
sample an output of the analog-to-digital converter during the voltage drop; and
compute a relative voltage drop value comprising subtracting the sampled output of the analog-to-digital converter during the voltage drop from a sampled output of the analog-to-digital converter during a steady-state condition, the current sink operating at the set point during the steady-state condition and during the voltage drop.

### Claim 10 (depends on 9)

The circuit of claim 9, wherein the current sink comprises a digital-to-analog converter (ADC) and a load.

### Claim 11 (depends on 9)

The circuit of claim 9, wherein the determining the set point for the current sink comprises:
sampling a first output of the analog-to-digital converter during a second steady-state condition, the current sink disabled during the second steady-state condition; and
selectively adjusting an amount of current sunk through the current sink until the output of the analog-to-digital converter is at a targeted value relative to the first output.

### Claim 12 (depends on 11)

The circuit of claim 11, wherein the selectively adjusting the amount of current sunk through the current sink comprises:
monitoring the output of the analog-to-digital converter;
adjusting the amount of current sunk by a control signal generated by the controller based on monitoring the output of the analog-to-digital converter; and
communicating the control signal to a digital-to-analog converter (DAC) of the current sink.

### Claim 13 (depends on 9)

The circuit of claim 9, wherein the node is coupled to a discharge circuit, the voltage drop comprises enabling a discharge switch of the discharge circuit coupled to the node such that a voltage at the node drops in value.

### Claim 14 (depends on 9)

The circuit of claim 9, wherein the controller is further configured to compute a voltage drop value at the node based on a linear relationship between the voltage drop and the relative voltage drop value.

### Claim 15 (depends on 9)

The circuit of claim 9, wherein the set point is chosen to prevent the analog-to-digital converter from saturating.

### Claim 16 (depends on 9)

The circuit of claim 9, wherein the analog-to-digital converter is a sigma-delta (Σ-Δ) and the controller is a proportional-integral-derivative (PID) controller.

### Claim 17 (depends on 9)

The circuit of claim 9, wherein the node is a node of a reserve capacitor in a supplemental restraint system (SRS) of a vehicle.

### Claim 18

A system, comprising:
a capacitor having a first node;
an analog-to-digital converter (ADC) coupled to the first node;
a current sink coupled to the first node and an input of the analog-to-digital converter, the current sink configured to be adjusted via a control signal to selectively adjust an amount of current sunk through the current sink; and
a controller coupled to an output of the analog-to-digital converter and a control input of the current sink, the controller configured to:
determine a set point for the current sink;
sample an output of the analog-to-digital converter during a voltage drop at the first node; and
compute a relative voltage drop value comprising subtracting the sampled output of the analog-to-digital converter during the voltage drop from a sampled output of the analog-to-digital converter during a steady-state condition, the current sink operating at the set point during the steady-state condition and during the voltage drop.

### Claim 19 (depends on 18)

The system of claim 18, wherein the determining the set point for the current sink comprises:
sampling a first output of the analog-to-digital converter during a second steady-state condition, the current sink disabled during the second steady-state condition; and
selectively adjusting an amount of current sunk through the current sink until the output of the analog-to-digital converter is at a targeted value relative to the first output.

### Claim 20 (depends on 19)

The system of claim 19, wherein the selectively adjusting the amount of current sunk through the current sink comprises:
monitoring the output of the analog-to-digital converter;
adjusting the amount of current sunk by a control signal generated by the controller based on monitoring the output of the analog-to-digital converter; and
communicating the control signal to a digital-to-analog converter (DAC) of the current sink.

### Claim 21 (depends on 18)

The system of claim 18, further comprising a discharge circuit coupled to the capacitor via the first node, the voltage drop comprises enabling a discharge switch of the discharge circuit coupled to the first node such that a voltage at the first node drops in value.

### Claim 22 (depends on 18)

The system of claim 18, wherein the set point is chosen to prevent the analog-to-digital converter from saturating.

### Claim 23 (depends on 18)

The system of claim 18, wherein the capacitor is a reserve capacitor of a supplemental restraint system (SRS) of a vehicle.
