# US 2023/0054942 A1 · Systems and methods for stalling host processor > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2023/0054942 A1 - Document ID: US20230054942A1 - Status: Published application - Kind: A1 - Application number: 17/880,539 - Filed: 2022-08-03 - Published: 2023-02-23 - Earliest claimed: 2018-11-06 - Assignees: Dover Microsystems, Inc. - Applicants: Dover Microsystems, Inc. - Inventors: Steven Milburn; Gregory T. Sullivan - Web page: https://patentgrep.com/patent/US20230054942A1 ## CPC - G06F 9/4812: {by interrupt, e.g. masked} - G06F 21/554: {involving event detection and direct action} - G06F 9/30043: {LOAD or STORE instructions; Clear instruction} - G06F 9/3013: {according to data content, e.g. floating-point registers, address registers} - G06F 13/24: using interrupt (G06F13/32 takes precedence) - G06F 21/121: {Restricting unauthorised execution of programs} - G06F 21/52: during program execution, e.g. stack integrity {; Preventing unwanted data erasure; Buffer overflow} - G06F 21/56: Computer malware detection or handling, e.g. anti-virus arrangements - G06F 21/75: by inhibiting the analysis of circuitry or operation - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract Systems and methods for stalling a host processor. In some embodiments, the host processor may be caused to initiate one or more selected transactions, wherein the one or more selected transactions comprise a bus transaction. The host processor may be prevented from completing the one or more selected transactions, to thereby stall the host processor. ## Claims ### Claim 1 A method for stalling a host processor, the method comprising acts of: causing the host processor to initiate one or more selected transactions, wherein the one or more selected transactions comprise a bus transaction; and preventing the host processor from completing the one or more selected transactions, to thereby stall the host processor. ### Claim 2 (depends on 1) The method of claim 1, wherein: the host processor communicates with a downstream component via a communication path; the bus transaction is initiated on a bus that is outside the communication path between the host processor and the downstream component; and the act of preventing the host processor from completing the one or more selected transactions is performed in response to determining that the downstream component is falling behind the host processor. ### Claim at position 3 -4. (canceled) ### Claim 5 (depends on 1) The method of claim 1, wherein: the act of causing the host processor to initiate one or more selected transactions comprises asserting an interrupt to cause the host processor to initiate the bus transaction, which comprises an operation with respect to a selected address. ### Claim 6 (canceled) ### Claim 7 (depends on 5) The method of claim 5, wherein: the selected address comprises an interrupt vector address corresponding to the interrupt; and the act of preventing the host processor from completing the bus transaction comprises preventing the host processor from loading, from the interrupt vector address, one or more instructions of an interrupt handler corresponding to the interrupt. ### Claim at position 7 -9. (canceled) ### Claim 10 (depends on 5) The method of claim 5, wherein: the selected address comprises an address of a selected register; and the act of preventing the host processor from completing the bus transaction comprises preventing the host processor from accessing the selected register. ### Claim 11 (depends on 1) The method of claim 1, further comprising an act of: detecting a trigger to stall the host processor, wherein the act of causing the host processor to initiate one or more selected transactions is performed in response to detecting the trigger to stall the host processor. ### Claim 12 (depends on 11) The method of claim 11, further comprising an act of: processing metadata associated with instructions executed by the host processor to check if the instructions are to be allowed, wherein the act of detecting a trigger to stall the host processor comprises determining that the metadata processing is falling behind the host processor's execution. ### Claim 13 (depends on 12) The method of claim 12, further comprising acts of: storing a result of the host processor's execution in a result queue while an instruction that produced the result is being checked; and in response to determining that the instruction is to be allowed, writing the result to an application memory, wherein the act of detecting a trigger to stall the host processor comprises determining that the result queue is filled to a selected threshold level. ### Claim 14 (depends on 12) The method of claim 12, further comprising an act of: storing instructions to be checked in an instruction queue, wherein the act of detecting a trigger to stall the host processor comprises determining that the instruction queue is filled to a selected threshold level. ### Claim 15 (canceled) ### Claim 16 (depends on 1) The method of claim 1, wherein: the act of causing the host processor to initiate one or more selected transactions comprises inserting, into object code, one or more instructions that, when executed by the host processor, cause the host processor to initiate the one or more selected transactions. ### Claim 17 (depends on 16) The method of claim 16, wherein: the one or more instructions are inserted into the object code at a frequency selected based on a capacity of a downstream component that consumes outputs of the host processor. ### Claim 18 (depends on 17) The method of claim 17, wherein: the capacity of the downstream component is selected based on a quantum of a pre-emptive operating system. ### Claim 19 (canceled) ### Claim 20 A method for stalling transactions on a first bus along a communication path between an upstream component and a downstream component, the method comprising acts of: causing the upstream component to initiate a transaction on a second bus, wherein the second bus is outside the communication path between the upstream component and the downstream component; and stalling the transaction on the second bus to thereby stall the upstream component. ### Claim 21 (depends on 20) The method of claim 20, wherein: the first bus does not provide a native stall signal. ### Claim 22 (depends on 21) The method of claim 21, wherein: the act of causing the upstream component to initiate a transaction on a second bus is performed in response to detecting that the downstream component is falling behind the upstream component. ### Claim 23 A system comprising circuitry and/or one or more processors programmed by executable instructions, wherein the circuitry and/or the one or more programmed processors are configured to perform a method for stalling a host processor, the method comprising acts of: causing the host processor to initiate one or more selected transactions, wherein the one or more selected transactions comprise a bus transaction; and preventing the host processor from completing the one or more selected transactions, to thereby stall the host processor. ### Claim 24 (depends on 23) At least one computer-readable medium having stored thereon at least one netlist for the circuitry of claim 23. ### Claim 25 (depends on 24) At least one computer-readable medium having stored thereon at least one hardware description that, when synthesized, produces the at least one netlist of claim 24. ### Claim 26 (depends on 25) The at least one computer-readable medium of claim 25, wherein the at least one hardware description is in an encrypted form. ### Claim 27 (depends on 23) At least one computer-readable medium having stored thereon the executable instructions of claim 23.