# US 2023/0054866 A1 · System and method to extend nvme queues to user space

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- Number: US 2023/0054866 A1
- Document ID: US20230054866A1
- Status: Published application
- Kind: A1
- Application number: 17/972,580
- Filed: 2022-10-24
- Published: 2023-02-23
- Earliest claimed: 2015-04-17
- Assignees: Samsung Electronics Co., Ltd.
- Applicants: Samsung Electronics Co., Ltd.
- Inventors: Oscar Prem PINTO
- Web page: https://patentgrep.com/patent/US20230054866A1

## CPC

- G06F 12/0238: {Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory}
- G06F 13/4282: {on a serial bus, e.g. I2C bus, SPI bus (on daisy chain buses G06F13/4247)}
- G06F 13/4068: {Electrical coupling}
- G06F 2212/1044: Space efficiency improvement
- G06F 2212/202: Non-volatile memory
- G06F 2212/7203: Temporary buffering, e.g. using volatile buffer or dedicated buffer blocks
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

An embodiment includes a system, comprising: a processor configured to: read a stride parameter from a device coupled to the processor; and map registers associated with the device into virtual memory based on the stride parameter; wherein: the stride parameter is configured to indicate a stride between the registers associated with the device; and the processor is configured to map at least one of the registers to user space virtual memory in response to the stride parameter.

## Claims

### Claim 1

A system, comprising:
a non-volatile memory express (NVMe) device comprising a memory and at least one pair of first registers that are mappable into a kernel space and at least one pair of second registers that are mappable into a user space, the pair of first registers comprising a submission queue register and a completion queue register, and the pair of second registers comprising a submission queue register and a completion queue register that are adjacent to one another in the user space; and
a processor coupled to a processor-local bus, the processor mapping the first registers into the kernel space and the second registers into the user space based on a distance parameter, the at least one pair of first registers being separated in kernel space by the distance parameter and the at least one pair of second registers being separated in user space by the distance parameter.