# US 2023/0054800 A1 · Wafer

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- Number: US 2023/0054800 A1
- Document ID: US20230054800A1
- Status: Published application
- Kind: A1
- Application number: 17/816,805
- Filed: 2022-08-02
- Published: 2023-02-23
- Earliest claimed: 2021-08-23
- Assignees: Shinko Electric Industries Co., Ltd.
- Applicants: Shinko Electric Industries Co., Ltd.
- Inventors: Kengo YAMAMOTO
- Web page: https://patentgrep.com/patent/US20230054800A1

## CPC

- H10W 72/0198: {batch processes}
- H10W 72/20: Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
- H10W 72/01235: {by plating, e.g. electroless plating or electroplating}
- H10W 72/01238: {in gaseous form, e.g. by CVD or PVD}
- H10W 72/01253: {by etching}
- H10W 72/01255: {by using masks}
- H10W 72/019: {of bond pads}
- H10W 72/222: {Multilayered bumps, e.g. a coating on top and side surfaces of a bump core}
- H10W 72/232: {Plan-view shape, i.e. in top view}
- H10W 72/248: {Top-view layouts, e.g. mirror arrays}
- H10W 72/252: {comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu}
- H10W 72/267: {Multiple bump connectors having different functions}
- H10W 72/90: Bond pads, in general
- H10W 72/923: {Bond pads having multiple stacked layers}
- H10W 72/9415: {relative to the surface, e.g. recessed, protruding}
- H10W 72/942: {relative to underlying supporting features, e.g. bond pads, RDLs or vias}
- H10W 72/9445: {Top-view layouts, e.g. mirror arrays}
- H10W 72/952: {comprising metals or metalloids, e.g. PbSn, Ag or Cu}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A wafer includes a substrate and conductive bumps on a surface of the substrate. In a plan view from a direction perpendicular to the surface of the substrate, the area density of the conductive bumps is higher in a first area than in a second area around the first area in the surface of the substrate. The first area has effective chip areas arranged therein.

## Claims

### Claim 1

A wafer comprising:
a substrate; and
a plurality of conductive bumps on a surface of the substrate,
wherein, in a plan view from a direction perpendicular to said surface of the substrate, an area density of the conductive bumps is higher in a first area than in a second area around the first area in said surface of the substrate, the first area having a plurality of effective chip areas arranged therein.

### Claim 2 (depends on 1)

The wafer as claimed in claim 1, wherein
the conductive bumps include a plurality of first conductive bumps in the first area and a plurality of second conductive bumps in the second area, and
an area density of the second conductive bumps in the second area is lower than an area density of the first conductive bumps in the first area in the plan view.

### Claim 3 (depends on 2)

The wafer as claimed in claim 2, wherein the area density of the second conductive bumps in the second area continuously decreases as a distance from the first area increases.

### Claim 4 (depends on 2)

The wafer as claimed in claim 2, wherein the area density of the second conductive bumps in the second area gradually decreases as a distance from the first area increases.

### Claim 5 (depends on 2)

The wafer as claimed in claim 2, wherein the area density of the second conductive bumps in the second area is 5% to 80% of the area density of the first conductive bumps in the first area.

### Claim 6 (depends on 2)

The wafer as claimed in claim 2, wherein each of the first conductive bumps and each of the second conductive bumps are equal in equivalent circle diameter in the plan view.

### Claim 7 (depends on 2)

The wafer as claimed in claim 2, wherein a number density of the second conductive bumps in the second area is lower than a number density of the first conductive bumps in the first area in the plan view.

### Claim 8 (depends on 1)

The wafer as claimed in claim 1, wherein each of the conductive bumps includes a copper pillar.

### Claim 9 (depends on 1)

The wafer as claimed in claim 1, wherein the conductive bumps are provided one on each of a plurality of electrode pads on the substrate.

### Claim 10 (depends on 9)

The wafer as claimed in claim 9, wherein the electrode pads include aluminum.

### Claim 11 (depends on 9)

The wafer as claimed in claim 9, wherein the conductive bumps include a seed layer on the electrode pads.

### Claim 12 (depends on 11)

The wafer as claimed in claim 11, wherein the seed layer includes copper, titanium, chromium, tungsten, or an alloy of any combination thereof.